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FS7140-01-XTD(16SOIC) 参数 Datasheet PDF下载

FS7140-01-XTD(16SOIC)图片预览
型号: FS7140-01-XTD(16SOIC)
PDF下载: 下载PDF文件 查看货源
内容描述: [Clock Generator,]
分类和应用:
文件页数/大小: 15 页 / 977 K
品牌: AMI [ AMI SEMICONDUCTOR ]
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Data Sheet  
FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator  
IN  
SS  
OUT  
X to V . Do not connect to X  
.
Then:  
When not using the REF input, it is preferred to leave it floating  
R1 (from CLKP and CLKN output to VDD) =  
DD  
LOAD  
DD  
HI  
or connected to V .  
R
* V / V =  
75 * 3.3 / 2.4 =  
103 ohms  
4.1.6 Feedback Divider Source MUX  
The source of frequency for the feedback divider may be  
selected to be either the output of the post divider or the output  
of the VCO by the FBKDSRC bit.  
R2 (from CLKP and CLKN output to GND) =  
LOAD  
DD  
DD  
HI  
R
* V / (V - V ) =  
75 * 3.3 / (3.3 - 2.4) =  
275 ohms  
Ordinarily, for frequency synthesis, the output of the VCO is  
used. Use the output of the post divider only where a  
deterministic phase relationship between the output clock and  
reference clock are desired (line-locked mode, for example).  
Rprgm (from VDD to IPRG pin) =  
DD  
LOAD  
HI  
LO  
26 * (V * R ) / (V - V ) / 3 =  
26 * (3.3 * 75) / (2.4 - 1.6) / 3 =  
2.68 Kohms  
4.1.7 Device Shutdown  
Two bits are provided to effect shutdown of the device if  
desired, when it is not active. SHUT1 disables most externally  
4.3 SYNC Circuitry  
observable device functions.  
quiescent current to absolute minimum values. Normally, both  
bits should be set or cleared together.  
SHUT2 reduces device  
The FS7145 supports nearly instantaneous adjustment of the  
output CLK phase by the SYNC input. Either edge direction of  
SYNC (positive-going or negative-going) is supported.  
Serial communications capability is not disabled by either  
SHUT1 or SHUT2.  
Example (positive-going SYNC selected): Upon the negative  
edge of SYNC input, a sequence begins to stop the CLK  
output. Upon the positive edge, CLK resumes operation,  
synchronized to the phase of the SYNC input (plus a  
deterministic delay). This is performed by control of the device  
post-divider. Phase resolution equal to ½ of the VCO period  
can be achieved (approximately down to 2ns).  
4.2 Differential Output Stage  
The differential output stage supports both CMOS and pseudo-  
ECL (PECL) signals. The desired output interface is chosen via  
the programming registers.  
5.0 I2C-bus Control Interface  
If a PECL interface is used, the transmission line is usually  
terminated using a Thévenin termination. The output stage can  
only sink current in the PECL mode, and the amount of sink  
current is set by a programming resistor on the LOCK/IPRG  
pin. The ratio of output sink current to IPRG current is 13:1.  
Source current for the CLKx pins is provided by the pull-up  
resistors that are part of the Thévenin termination.  
This device is a read/write slave device meeting all  
Philips I2C-bus specifications except a "general  
call." The bus has to be controlled by a master  
device that generates the serial clock SCL,  
controls bus access and generates the START  
and STOP conditions while the device works as a slave. Both  
master and slave can operate as a transmitter or receiver, but  
the master device determines which mode is activated. A  
device that sends data onto the bus is defined as the  
transmitter, and a device receiving data as the receiver.  
4.2.1 Example  
Assume that it is desired to connect a PECL-type fanout buffer  
right next to the FS7140.  
I2C-bus logic levels noted herein are based on a percentage of  
Further assume:  
DD  
· V = 3.3V  
DD  
the power supply (V ). A logic-one corresponds to a nominal  
HI  
· desired V = 2.4V  
DD  
SS  
voltage of V , while a logic-zero corresponds to ground (V ).  
LO  
· desired V = 1.6V  
LOAD  
· equivalent R  
= 75 ohms  
AMI Semiconductor - Rev. 3.0  
www.amis.com  
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