Data Sheet
FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator
Table 12: DC Electrical Specifications
Parameter
Overall
Symbol Conditions/Description
Min.
Typ.
Max.
Units
XTAL
VCO
CMOS mode; F
= 15MHz; F = 400MHz;
DD
I
I
Supply Current, Dynamic
35
mA
CLK
F
= 200MHx; does not include load current
DDL
Supply Current, Static
SHUT1, SHUT2 bit both “1”
400
700
µA
Serial Communication I/O (SDA, SCL)
High-Level Input Voltage
IH
DD
V
V
V
0.8*V
V
IL
DD
0.2*V
+10
Low-Level Input Voltage
V
hys
DD
0.33*V
14
Hysteresis Voltage
V
I
I
Input Leakage Current
SDA, SCL in read condition
-10
5
µA
mA
OL
SDA
I
SDA in acknowledge condition; V = 0.4V
Low-Level Output Sink Current (SDA)
Address Select Input (ADDR0, ADDR1)
High-Level Input Voltage
IH
IL
VDD
V
V
V
-1.0
-1.0
-1.0
V
Low-Level Input Voltage
0.8
1
V
IH
ADDRx
ADDRx
DD
I
I
V
= V
High-Level Input Current (pull-down)
Low-Level Input Current
30
µA
µA
IL
V
= 0V
-1
Reference Frequency Input (REF)
High-Level Input Voltage
IH
VDD
V
V
V
V
IL
Low-Level Input Voltage
0.8
1
V
IH
IL
REF
V
DD
= V
I
I
High-Level Input Current
-1
µA
µA
REF
V
= 0V
Low-Level Input Current (pull-down)
Sync Control Input (SYNC)
High-Level Input Voltage
-30
-30
IH
VDD
V
V
V
V
IL
Low-Level Input Voltage
0.8
1
V
IH
REF
REF
DD
I
I
V
= V
High-Level Input Current
-1
µA
µA
IL
V
= 0V
Low-Level Input Current (pull-down)
Crystal Oscillator Input (XIN)
Threshold Bias Voltage
TH
DD
V /2
V
V
IH
XIN
XIN
I
V
= VDD
= GND
High-Level Input Current
40
µA
µA
MHz
pF
IL
I
V
Low-Level input Current
-40
X
F
Crystal Frequency
Fundamental mode
35
10
L(XTAL)
C
Recommended Crystal Load Capacitance*
Crystal Oscillator Output (XOUT)
High-Level Output Source Current
Low-Level Output Sink Current
PECL Current Program I/O (IPRG)
Low-Level Input Current
For best matching with internal crystal oscillator load
16-18
OH
XOUT
V
I
I
= 0
-8.5
11
mA
mA
OL
XOUT
IPRG
O
V
= VDD
IL
I
V
= 0V; PECL Mode
-10
µA
Clock Outputs, CMOS Mode (CLKN, CLKP)
High-Level Output Source Current
Low-Level Output Sink Current
Clock Outputs, PECL Mode (CLKN, CLKP)
OH
OL
I
I
V = 2.0V
19
mA
mA
O
V = 0.4V
-35
IPRG
V
will be clamped to this level when a resistor is
IPRG
V
IPRG Bias Voltage
VDD/3
13
V
connected from VDD to IPRG
IPRG
IPRG
I
VDD
IPRG
SET
I
- (V - V ) / R
IPRG Bias Current
Sink Current to IPRG Current Ratio
Tristate Output Current
DD
3.5
10
mA
Z
I
-10
µA
A
Unless otherwise stated, V = 3.3V ± 10%, no load on any output, and ambient temperature range T = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data
and are not production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical. Negative currents indicate current flows out of the device.
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