Data Sheet
FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator
Table 13: AC Timing Specifications
Clock
(MHz)
Parameter
Overall
Symbol
Conditions/Description
Min. Typ.
Max.
Units
CMOS outputs
PECL outputs
0
0
150
300
400
O(max)
f
Output Frequency*
MHz
VCO
f
VCO Frequency*
40
MHz
ns
r
t
L
C = 7pF
CMOS Mode Rise Time*
CMOS Mode Fall Time*
PECL Mode Rise Time*
PECL Mode Fall Time*
Reference Frequency Input (REF)
Input Frequency
1
f
L
t
C = 7pF
1
ns
r
t
L
L
C = 7pF; R = 65 ohm
1
ns
f
L
L
t
C = 7pF; R = 65 ohm
1
ns
REF
F
80
MHz
ns
REHF
t
Reference High Time
3
3
REFL
t
Reference Low Time
ns
Sync Control Input (SYNC)
Sync High Time
SYNCH
CLK
t
T
for orderly CLK stop/start
for orderly CLK stop/start
3
3
SYNCL
CLK
t
T
Sync Low Time
Clock Output (CLKP, CLKN)
Duty Cycle (CMOS Mode)*
Duty Cycle (PECL Mode)*
Measured at 1.4V
50
50
%
%
CLKP
CLKN
Measured at zero crossings of (V -V
)
For valid programming solutions. Long-term (or cumulative) jitter specified is RMS
position error of any edge compared with an ideal clock generated from the same
reference frequency. It is measured with a time interval analyzer using a 500
microsecond window, using statistics gathered over 1000 samples.
ps
FREF/NREF > 1000kHz
FREF/NREF ~= 500kHz
FREF/NREF ~= 250kHz
FREF/NREF ~= 125kHz
FREF/NREF ~= 62.5kHz
FREF/NREF ~= 31.5kHz
40MHz < VCO Frequency < 100MHz
VCO Frequency > 100MHz
25
50
ps
ps
ps
ps
ps
ps
ps
ps
j(LT)
Jitter, Long Term (σ
γ
(τ))∗
t
100
190
240
300
75
j(∆P)
t
Jitter, Period (peak-peak)*
50
DD
A
Unless otherwise stated, V = 3.3V ± 10%, no load on any output, and ambient temperature range T = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data
and are not production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical.
Table 14: Serial Interface Timing Specifications
Fast Mode
Parameter
Symbol
Conditions/Description
Units
Min.
0
Max.
SCL
f
Clock Frequency
SCL
400
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
BUF
t
Bus Free Time Between STOP and START
Setup Time, START (repeated)
Hold Time, START
1300
600
600
100
0
su:STA
t
hd:STA
t
su:DAT
t
Setup Time, Data Input
Hold Time, Data Input
SDA
SDA
hd:DAT
t
AA
t
Output Data Valid From Clock
Rise Time, Data and Clock
Fall Time, Data and Clock
High Time, Clock
900
300
300
R
t
SDA, SCL
SDA, SCL
SCL
F
t
HI
t
600
1300
600
LO
t
Low Time, Clock
SCL
su:STO
t
Setupt Time, STOP
DD
A
Unless otherwise stated, V = 3.3V ± 10%, no load on any output, and ambient temperature range T = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data
and are not production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical.
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