F I N A L
SWITCHING CHARACTERISTICS
The switching characteristics given consist of output
delays, input setup requirements, and input hold re-
quirements. All switching characteristics are relative to
the CLK2 rising edge crossing the 2.0-V level.
window. Within the sampling window, a synchronous
input signal must be stable for correct operation.
Outputs ADS, W/R, D/C, M/IO, LOCK, BHE, BLE,
A23–A1, HLDA, and SMIADS* only change at the be-
ginning of phase one. D15–D0 and SMI* write cycles
only change at the beginning of phase two. The
READY, HOLD, BUSY, ERROR, PEREQ, FLT, D15–
D0, IIBEN*, and SMIRDY* read cycles inputs are sam-
pled at the beginning of phase one. The NA, INTR,
NMI, and SMI* inputs are sampled at the beginning of
phase two.
Switching characteristic measurement is defined in
Figure 2. Inputs must be driven to the voltage levels in-
dicated by Figure 2 when switching characteristics are
measured. Output delays are specified with minimum
and maximum limits measured, as shown. The mini-
mum delay times are hold times provided to external
circuitry. Input setup and hold times are specified as
minimums, defining the smallest acceptable sampling
* – On Am386SXLV only; NC on Am386SX/SXL
Tx
φ
φ 1
2
2 V
CLK2
A
B
Min
Max
(A23–A1, BHE, BLE,
ADS, M/IO, D/C,
W/R, LOCK, HLDA,
SMIADS*)
Valid
Output n
Valid
Output n+1
VT
VT
A
B
Min
Max
Valid
Output n
VT
VT
Valid
Output n+1
(D15–D0, SMI*)
C
D
Valid
Input
(NA, INTR, NMI, SMI*)
VT
VT
C
D
(READY, HOLD,
FLT, ERROR, BUSY,
PEREQ, D15–D0,
Valid
Input
VT
VT
IIBEN*, SMIRDY*)
Legend: A–Maximum Output Delay Characteristic
B–Minimum Output Delay Characteristic
C–Minimum Input Setup Characteristic
D–Minimum Input Hold Characteristic
Notes:
1. Input waveforms have tr ≤ 2.0 ns from 0.8 V–2.0 V (on Am386SXLV only).
2. On Am386SX/SXL, VT = 1.5; on Am386SXLV, VT = 1.0 V for VCC ≤ 3.6 V and 1.5 V for VCC > 3.6 V.
3. * = On Am386SXLV only.
16305C–003
Figure 2. Drive Levels and Measurement Points for Switching Characteristics
Am386SX/SXL/SXLV Microprocessors Data Sheet
14
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