F I N A L
PIN DESCRIPTIONS
A23–A1
HOLD
Address Bus (Outputs)
Bus Hold Request (Active High; Input)
Outputs physical memory or port I/O addresses.
Input allows another bus master to request control of
the local bus.
ADS
Address Status (Active Low; Output)
IIBEN (Am386SXLV Only)
I/O Instruction Break Enable (Active Low; Input)
Indicates that a valid bus cycle definition and address
(W/R, D/C, M/IO, BHE, BLE, and A23–A1) are being
driven at the Am386SX/SXL/SXLV microprocessor
pins. Bus cycles initiated by ADS must be terminated
by READY.
Enables the I/O instruction break feature. IIBEN has a
dynamic internal pull-up resistor. The IIBEN pull-up is
active during RESET and whenever the signal is not
driven active Low by the system.
BHE, BLE
INTR
Byte Enables (Active Low; Outputs)
Interrupt Request (Active High; Input)
Indicate which data bytes of the data bus take part in a
bus cycle.
A maskable input that signals the Am386SX/SXL/
SXLV microprocessor to suspend execution of the cur-
rent program and execute an interrupt acknowledge
function.
BUSY
Busy (Active Low; Input)
LOCK
Signals a busy condition from a processor extension.
BUSY has an internal pull-up resistor.
Bus Lock (Active Low; Output)
A bus cycle definition pin that indicates that other sys-
tem bus masters are not to gain control of the system
bus while it is active.
CLK2
CLK2 (Input)
Provides the fundamental timing for the Am386SX/
SXL/SXLV microprocessor.
M/IO
Memory/IO (Output)
D15–D0
Data Bus (Inputs/Outputs)
A bus cycle definition pin that distinguishes memory cy-
cles from input/output cycles.
Inputs data during memory, I/O, and interrupt acknowl-
edge read cycles; outputs data during memory and I/O
write cycles.
NA
Next Address (Active Low; Input)
Used to request address pipelining.
D/C
Data/Control (Output)
NC
No Connect
A bus cycle definition pin that distinguishes data cy-
cles, either memory or I/O, from control cycles which
are interrupt acknowledge, halt, and code fetch.
Should always be left unconnected. Connection of an
NC pin may cause the processor to malfunction or be
incompatible with future steppings of the Am386SX/
SXL/SXLV microprocessor.
ERROR
Error (Active Low; Input)
NMI
Signals an error condition from a processor extension.
ERROR has an internal pull-up resistor.
Non-Maskable Interrupt Request
(Active High; Input)
FLT
A non-maskable input that signals to the Am386SX/
SXL/SXLV microprocessor to suspend execution of the
current program and execute an interrupt acknowledge
function.
Float (Active Low; Input)
An input which forces all bidirectional and output sig-
nals, including HLDA, to the three-state condition. FLT
has an internal pull-up resistor. The pin, if not used,
should be disconnected.
PEREQ
Processor Extension Request (Active High; Input)
HLDA
Indicates that the processor has data to be transferred
by the Am386SX/SXL/SXLV microprocessor. PEREQ
has an internal pull-down resistor.
Bus Hold Acknowledge (Active High; Output)
Output indicates that the Am386SX/SXL/SXLV micro-
processor has surrendered control of its logical bus to
another bus master.
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Am386SX/SXL/SXLV Microprocessors Data Sheet
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