F I N A L
SWITCHING CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges
at 25 MHz
VCC = 5.0 V ± 10%; TCASE = 0°C to +100°C (Commercial); TCASE = –40°C to +100°C (Industrial)
VCC = 3.0 V–5.5 V; TCASE = 0°C to +100°C (Am386SXLV only)
Final
Figures Min Max Unit
Ref.
Symbol
Parameter Description
Operating Frequency: Am386SX CPU
Notes
Half CLK2 freq.
Half CLK2 freq.
2
0
25
25
MHz
Am386SXL/SXLV CPU
1
2
2a
2b
3
CLK2 Period
3, 4
3
4
4
3
4
4
4
3
4
3
8
15
8
15
8
8
15, 18
15
8, 9
10
15
8
20
4
7
4
5
ns
ns
ns
ns
ns
ns
ns
CLK2 High Time:
CLK2 High Time:
CLK2 High Time:
CLK2 Low Time:
CLK2 Low Time:
CLK2 Low Time:
CLK2 Fall Time:
Am386SXLV CPU
Am386SX/SXL CPU
Am386SX/SXL CPU
Am386SXLV CPU
Am386SX/SXL CPU
Am386SX/SXL CPU
Am386SX/SXL CPU
Am386SXLV CPU
Am386SX/SXL CPU
Am386SXLV CPU
at VIHC
at 2 V
at (VCC–0.8 V)
at 0.8 V
at 2 V
at 0.8 V
(VCC–0.8 V) to 0.8 V (Note 3)
2.4 V to 0.8 V
3a
3b
7
5
4
5
7
7
ns
ns
(Note 3)
(Note 3)
CLK2 Rise Time:
0.8 V to 2.4 V
0.8 V to (VCC–0.8 V) (Note 3)
CL = 50 pF
6
7
8
A23–A1 Valid Delay
A23–A1 Float Delay
BHE, BLE, LOCK Valid Delay
BHE, BLE, LOCK Float Delay
M/IO, D/C, W/R, ADS Valid Delay
SMIADS Valid Delay
W/R, M/IO, D/C, ADS Float Delay
SMIADS Float Delay
D15–D0 Write Data Valid Delay
D15–D0 Write Data Hold Time
D15–D0 Write Data Float Delay
HLDA Valid Delay
4
4
4
4
4
4
4
4
7
2
4
4
4
4
5
3
9
9
4
4
7
5
9
3
8
3
6
6
6
4
6
5
4
4
17
30
17
30
17
25
30
30
23
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(Note 1)
CL = 50 pF
9
(Note 1)
10
10s
11
11s
12
12a
13
14
CL = 50 pF
CL = 50 pF
(Note 5)
(Note 1)
(Notes 1, 5)
CL = 50 pF
CL = 50 pF
(Note 1)
22
22
22
30
CL = 50 pF
HLDA Float Delay:
Am386SX/SXL
Am386SXLV
14f
15, 16
ns
(Notes 1, 4)
15
16
19
19s
20
20s
21
22
23
24
25
26
27
27s
28
28s
29
30
31
32
NA Setup Time
NA Hold Time
7
7
7
7
7
7
7
7
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
READY Setup Time
SMIRDY Setup Time
READY Hold Time
SMIRDY Hold Time
D15–D0 Read Data Setup Time
D15–D0 Read Data Hold Time
HOLD Setup Time
HOLD Hold Time
RESET Setup Time
RESET Hold Time
NMI, INTR Setup Time
SMI Setup Time
NMI, INTR Hold Time
SMI Hold Time
PEREQ, ERROR, BUSY, FLT, IIBEN5 Setup Time
PEREQ, ERROR, BUSY, FLT, IIBEN5 Hold Time
SMI Valid Delay
(Note 5)
(Note 5)
7
17
17
7
7
7
7
7
7
8, 15
16
(Note 2)
(Note 5)
(Note 2)
(Note 5)
(Note 2)
(Note 2)
(Note 5)
22
30
SMI Float Delay
(Notes 1, 4, 5)
Notes:
1. Float condition occurs when maximum output current becomes less than ILO in magnitude. Float delay is not 100% tested.
2. These inputs are allowed to be asynchronous to CLK2. The setup and hold specifications are given for testing purposes, to
assure recognition within a specific CLK2 period.
3. Rise and Fall times are not tested. They are guaranteed by design characterization.
4. Only during FLT assertion.
5. On Am386SXLV only.
Am386SX/SXL/SXLV Microprocessors Data Sheet
15
AMD [ AMD ]
