F I N A L
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges at 40 MHz
VCC = 5.0 V ± 5%; TCASE = 0°C to +100°C (Am386SX only)
Final
Figures Min Max Unit
40 MHz
Ref.
Symbol
Parameter Description
Operating Frequency
Notes
Half CLK2 frequency
2
1
2
3
4
5
6
7
8
9
CLK2 Period
CLK2 High Time
CLK2 Low Time
CLK2 Fall Time
CLK2 Rise Time
A23–A1 Valid Delay
A23–A1 Float Delay
BHE, BLE, LOCK Valid Delay
BHE, BLE, LOCK Float Delay
M/IO, D/C, W/R, ADS Valid Delay
W/R, M/IO, D/C, ADS Float Delay
D15–D0 Write Data Valid Delay
D15–D0 Write Data Hold Time
D15–D0 Write Data Float Delay
HLDA Valid Delay
HLDA Float Delay
NA Setup Time
NA Hold Time
READY Setup Time
5
5
5
5
5
8
15
8
15
8
15
8
10
15
15
15
7
7
7
7
7
12.5 250
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
at 2.7 V
at 0.8 V
2.7 V to 0.8 V
0.8 V to 2.7 V
CL = 50 pF
4.5
4.5
4
(Note 3)
(Note 3)
4
4
4
4
4
4
4
7
2
4
4
4
5
2
7
4
4
3
4
2
4
2
5
5
5
4
13
20
13
20
13
20
18
(Note 1)
(Note 1)
CL = 50 pF
CL = 50 pF
10
11
12
12a
13
14
14f
15
16
19
20
21
22
23
24
25
26
27
28
29
30
Notes:
(Note 1)
(Note 4)
CL = 50 pF
CL = 50 pF
(Note 1)
17
17
17
CL = 50 pF
READY Hold Time
D15–D0 Read Data Setup Time
D15–D0 Read Data Hold Time
HOLD Setup Time
HOLD Hold Time
RESET Setup Time
7
7
7
17
17
7
7
7
RESET Hold Time
NMI, INTR Setup Time
NMI, INTR Hold Time
PEREQ, ERROR, BUSY, FLT Setup Time
PEREQ, ERROR, BUSY, FLT Hold Time
(Note 2)
(Note 2)
(Note 2)
(Note 2)
7
1. Float condition occurs when maximum output current becomes less than ILO in magnitude. Float delay is not 100% tested.
2. These inputs are allowed to be asynchronous to CLK2. The setup and hold specifications are given for testing purposes, to
assure recognition within a specific CLK2 period.
3. Rise and Fall times are not tested. They are guaranteed by design characterization.
4. Min time is not 100% tested.
Am386SX/SXL/SXLV Microprocessors Data Sheet
17
AMD [ AMD ]
