F I N A L
croprocessor pins while in the System Management
READY
Bus Ready (Active Low; Input)
mode. Bus cycles initiated by SMIADS must be termi-
nated by SMIRDY.
Terminates the bus cycle initiated by ADS.
SMIRDY (Am386SXLV Only)
SMI Ready (Active Low; Input)
RESET
Reset (Active High; Input)
This input terminates the current bus cycle to the SMM
mode address space in the same manner the READY
pin does for the normal mode address space. SMIRDY
has an internal pull-up resistor. READY and SMIRDY
must not be tied together.
Suspends any operation in progress and places the
Am386SX/SXL/SXLV microprocessor in a known reset
state.
SMI (Am386SXLV Only)
System Management Interrupt (Active Low; I/O)
VCC
A non-maskable interrupt pin that signals to the
Am386SXLV microprocessor to suspend execution
and enter System Management Mode. SMI has an in-
ternal pull-up resistor. SMI has a dynamic internal
pull-up resistor that is disabled when the processor is
in SMM. SMI is not three-stated during Hold Acknowl-
edge bus cycles.
System Power (Input)
Provides the 5 V nominal DC supply input.
VSS
System Ground (Input)
Provides the 0-V connection from which all inputs and
outputs are measured.
SMIADS (Am386SXLV Only)
SMI Address Status (Active Low; Output)
W/R
Write/Read (Output)
When active, this pin indicates that a valid bus cycle
definition and address (W/R, D/C, M/IO, BHE, BLE,
and A23–A1) are being driven at the Am386SXLV mi-
A bus cycle definition pin that distinguishes write cycles
from read cycles.
LOGIC SYMBOL
2X Clock
CLK2
D15–D0
16
Data Bus
A23–A1
23
2
Address
Bus
FLT
Float
BLE, BHE
RESET
NMI
Interrupt
Control
INTR
ADS
NA
Bus
Cycle
Control
Am386SXLV
Microprocessor
READY
PEREQ
Math
BUSY
Coprocessor
Control
W/R
D/C
ERROR
Bus
Cycle
Definition
M/IO
LOCK
SMI
System
Management
Mode
SMIADS
SMIRDY
IIBEN
Control*
HOLD
HLDA
Bus Arbitration
*On Am386SXLV only
Control
16305C–003
Am386SX/SXL/SXLV Microprocessors Data Sheet
11
AMD [ AMD ]
