F I N A L
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges at 33 MHz
VCC = 5.0 V ± 10%; TCASE = 0°C to +100°C
Final
Figures Min Max Unit
Ref.
Symbol
Parameter Description
Notes
Half CLK2 freq.
Half CLK2 freq.
Operating Frequency: Am386SX CPU
Am386SXL CPU
2
0
33
33
MHz
1
2a
2b
3a
3b
4
CLK2 Period
4
4
15
6.25
4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLK2 High Time
at 2 V
CLK2 High Time
at 3.7 V
4
CLK2 Low Time
at 2 V
4
6.25
4.5
CLK2 Low Time
at 0.8 V
4
CLK2 Fall Time
3.7 V to 0.8 V
0.8 V to 3.7 V
CL = 50 pF
(Note 3)
(Note 3)
4
4
5
CLK2 Rise Time
4
4
6
A23–A1 Valid Delay
8
4
4
4
4
4
4
7
2
4
4
4
5
2
7
4
5
3
9
2
5
2
5
5
5
4
15
20
15
20
15
20
23
7
A23–A1 Float Delay
(Note 1)
(Note 1)
(Note 1)
15
8
8
BHE, BLE, LOCK Valid Delay
BHE, BLE, LOCK Float Delay
M/IO, D/C, W/R, ADS Valid Delay
W/R, M/IO, D/C, ADS Float Delay
D15–D0 Write Data Valid Delay
D15–D0 Write Data Hold Time
D15–D0 Write Data Float Delay
HLDA Valid Delay
CL = 50 pF
CL = 50 pF
9
15
8
10
11
12
12a
13
14
14f
15
16
19
20
21
22
23
24
25
26
27
28
29
30
Notes:
15
8
CL = 50 pF
CL = 50 pF
10
15
8
(Note 1)
17
20
20
CL = 50 pF
HLDA Float Delay
15
7
NA Setup Time
NA Hold Time
7
READY Setup Time
7
READY Hold Time
7
D15–D0 Read Data Setup Time
D15–D0 Read Data Hold Time
HOLD Setup Time
7
7
7
HOLD Hold Time
7
RESET Setup Time
17
17
7
RESET Hold Time
NMI, INTR Setup Time
NMI, INTR Hold Time
PEREQ, ERROR, BUSY Setup Time
PEREQ, ERROR, BUSY Hold Time
(Note 2)
(Note 2)
(Note 2)
(Note 2)
7
7
7
1. Float condition occurs when maximum output current becomes less than ILO in magnitude. Float delay is not 100% tested.
2. These inputs are allowed to be asynchronous to CLK2. The setup and hold specifications are given for testing purposes, to
assure recognition within a specific CLK2 period.
3. Rise and Fall times are not tested. They are guaranteed by design characterization.
4. Min time is not 100% tested.
16
Am386SX/SXL/SXLV Microprocessors Data Sheet
AMD [ AMD ]
