RESET
(Wakeup)
t1
Intermediate PLL
Lock
t2
Low-Speed PLL
Lock
t3
High-Speed PLL
Lock
t4
PLLRATIO[2:0]
Graphics Dot Clock
PLL Lock
Figure 13. PLL Enabling Timing Sequence
Table 32. PLL Jitter Specification
PLL
Min
Typ
Max
Unit
MHz
ns
Intermediate PLL frequency
Intermediate PLL cycle-to-cycle jitter
Low-Speed PLL frequency
1.4524
1.47456
1.4967
20.4
36.311
–1.5%
65.360
36.864
Target
37.417
0.82
MHz
ns
Low-Speed PLL cycle-to-cycle jitter
Graphics Dot Clock PLL frequency
Graphics Dot Clock PLL cycle-to-cycle jitter
High-Speed PLL frequency
+1.5%
1
MHz
ns
66.3552
67.351
0.5
MHz
ns
High-Speed PLL cycle-to-cycle jitter
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
85
AMD [ AMD ]
