Table 19. Signal Description Table (Continued)
Description
Signal
Clocks
Type
32KXTAL1
32KXTAL2
32.768-kHz Crystal Interface Signals are used for the 32.768-kHz crystal. This is the main
clock source for the chip and drives the internal Phase-Locked Loops (PLLs) that generate
all other clock frequencies needed in the system.
CLK_IO
I/O
A
Clock Input/Output is an input to drive the integrated 8254 timer with a 1.19318-MHz clock
signal from an external source, or an output to bring out certain internal clock sources to drive
external devices.
LF_INT, LF_LS,
LF_VID, LF_HS
Loop Filters connect external RC loop filters required by the internal PLLs. LF_VID is not
supported on the ÉlanSC410 microcontroller.
Parallel Port (Note: The names in parentheses in this section are those used in EPP mode.)
ACK (INTR)
I
Printer Acknowledge: In standard mode, this signal is driven by the parallel port device with
the state of the printer acknowledge signal. In EPP mode, this signal indicates to the chip that
the parallel port device has generated an interrupt request.
AFDT (DSTRB)
O
Auto Line Feed Detect: In standard mode, this signal is driven by the chip indicating to the
parallel port device to insert a line feed at the end of every line. In EPP mode, this signal is
driven active by the chip during reads or writes to the EPP data registers.
BUSY (WAIT)
ERROR
I
I
Printer Busy: In standard mode, this signal is driven by the parallel port device with the state
of the printer busy signal. In EPP mode, this signal adds wait states to the current cycle.
Error: The printer asserts this signal to inform the parallel port of a deselect condition, paper
end (PE) or other error condition.
INIT
O
I
Initialize Printer: This signals the printer to begin an initialization routine.
Paper End: The printer asserts this signal when it is out of paper.
PE
PPDWE
O
Parallel Port Write Enable controls an external 374 type latch in a unidirectional parallel port
design. This device latches the SD7–SD0 bus onto the parallel port data bus. To implement
a bidirectional parallel port, this pin can be reconfigured to act as an address decode for the
parallel port data port. PPDWE can then be externally gated with IOR and IOW to provide
the Parallel Port Data Read and Write Strobes, respectively.
PPOEN
O
Parallel Port Output Buffer Enable supports a bidirectional parallel port design. PPOEN
controls the output enable of the external Parallel Port Output Buffer (373 octal D-type
transparent latch).
SLCT
I
Printer Select is returned by a printer upon receipt of SLCTIN.
SLCTIN (ASTRB)
O
Printer Selected: In Standard mode, this signal is driven by the chip to select the parallel
port device. In EPP mode, this signal is driven active by the chip during reads or writes to the
EPP address register.
STRB (WRITE)
O
Strobe: In Standard mode, this signal indicates to the parallel port device to latch the data
on the parallel port data bus. In EPP mode, this signal is driven active during writes to the
EPP data or the EPP address register.
Serial Port
CTS
I
I
Clear To Send is driven back to the serial port to indicate that the external data carrier
equipment (DCE) is ready to accept data.
DCD
DSR
DTR
RIN
Data Carrier Detect is driven back to the serial port from a piece of data carrier equipment
when it has detected a carrier signal from a communications target.
I
Data Set Ready indicates that the external DCE is ready to establish a communication link
with the internal serial port controller.
O
I
Data Terminal Ready indicates to the external DCE that the internal serial port controller is
ready to communicate.
Ring Indicate is used by an external modem to inform the serial port that a ring signal was
detected. A change in state on this signal by the external modem can be configured to cause
a modem status interrupt. This signal can be used to cause the chip to resume from a
Suspend state.
66
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
AMD [ AMD ]
