SIGNAL DESCRIPTIONS
The descriptions in Table 19 are organized in
alphabetical order within the functional group listed here.
■ Serial Port on page 66
■ Keyboard Interfaces on page 67
■ General-Purpose Input/Output on page 67
■ Serial Infrared Port on page 67
■ System Interface on page 62
■ Configuration Pins on page 63
■ Memory Interface on page 64
■ VL-Bus Interface on page 64
■ Power Management on page 65
■ Clocks on page 66
■ PC Card Controller (ÉlanSC400 Microcontroller
Only) on page 67
■ LCD Graphics Controller (ÉlanSC400 Microcontrol-
ler Only) on page 68
■ Boundary Scan Test Interface on page 69
■ Reset and Power on page 69
■ Parallel Port on page 66
Table 19. Signal Description Table
Description
Signal
Type
System Interface
AEN
O
DMA Address Enable indicates that the current address active on the SA25–SA0 address
bus is a memory address, and that the current cycle is a DMA cycle. All I/O devices should
use this signal in decoding their I/O addresses, and should not respond when this signal is
asserted. When AEN is asserted, the PDACK1– PDACK0 signals are used to select the
appropriate I/O device for the DMA transfer. AEN is also asserted when a DMA cycle is
occurring internal to the chip.
On the ÉlanSC400 microcontroller, AEN is also asserted for all accesses to the PC Card I/O
space to prevent ISA devices from responding to the IOR/IOW signal assertions because
these signals are shared between the PC Card and ISA interfaces.
BALE
O
Bus Address Latch Enable is driven at the beginning of an ISA bus cycle with a valid
address. This signal can be used by external devices to latch the address for the current
cycle. BALE is also asserted for all accesses to the PC Card interfaces (memory or I/O)
(ÉlanSC400 microcontroller only) and all DMA cycles. This prevents an ISA device from
responding to a cycle based on a previously latched address.
DBUFOE
O
O
Data Buffer Output Enable controls the output enable on the external transceiver required
to drive the peripheral data bus in local bus and 32-bit DRAM modes.
DBUFRDH
High Byte Data Buffer Direction Control controls direction of data flow through the external
transceiver required to drive the peripheral data bus in local bus and 32-bit DRAM mode. This
is the control signal for the upper 8 bits of the data bus.
DBUFRDL
IOCHRDY
O
Low Byte Data Buffer Direction Control controls direction of data flow through the external
transceiver required to drive the peripheral data bus in local bus and 32-bit DRAM mode. This
is the control signal for the lower 8 bits of the data bus.
STI
PU
I/O Channel Ready should be driven by open-drain devices. When pulled Low during an ISA
access, wait states are inserted in the current cycle. This pin has an internal weak pullup that
should be supplemented by a stronger external pullup (usually 4.7 KΩ to 1 KΩ) for faster rise
time.
IOCS16
IOR
I
I/O Chip Select 16: The targeted I/O device drives this signal active early in the cycle to
request a 16-bit transfer.
O
I/O Read Command indicates that the current cycle is a read from the currently addressed
I/O device. When this signal is asserted, the selected I/O device can drive data onto the data
bus. This signal is also shared with the PC Card interface on the ÉlanSC400 microcontroller.
IOW
O
I
I/O Write Command indicates that the current cycle is a write to the currently addressed
I/O device. When this signal is asserted, the selected I/O device can latch data from the data
bus. This signal is also shared with the PC Card interface on the ÉlanSC400 microcontroller.
MCS16
Memory Chip Select 16 indicates to the ISA control logic that the targeted memory device
is a 16-bit-wide device.
62
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
AMD [ AMD ]
