Table 19. Signal Description Table (Continued)
Description
Signal
Type
MEMR
O
Memory Read Command indicates that the current cycle is a read of the currently
addressed memory device. When this signal is asserted, the memory device can drive data
onto the data bus.
MEMW
O
O
I
Memory Write Command indicates that the current cycle is a write of the currently
addressed memory device. When this signal is asserted, the memory device can latch data
from the data bus.
PDACK1–PDACK0
PDRQ1–PDRQ0
PIRQ7–PIRQ0
RSTDRV
Programmable DMA Acknowledge signals can each be mapped to one of the seven
available DMA channels. They are driven active (Low) back to the DMA initiator to
acknowledge the corresponding DMA requests.
Programmable DMA Requests can each be mapped to one of the seven available DMA
channels. They are asserted active (High) by a DMA initiator to request DMA service from
the DMA controller.
I
Programmable Interrupt Requests can each be mapped to one of the available 8259
interrupt channels. They are asserted when a peripheral requires interrupt service.
(Rising Edge/Active High Trigger)
O
O
System Reset is the ISA bus reset signal. When this signal is asserted, all connected
devices reinitialize to their reset state. This signal should not be confused with the internal
CPU RESET and SRESET signals.
SA25–SA0
System Address Bus outputs the physical memory or I/O port latched addresses. It is used
by all external peripheral devices other than main system DRAM. In addition, this is the local
address bus in local bus mode.
SBHE
O
B
System Byte High Enable is driven active when the high data byte is to be transferred on
the upper 8 bits of the ISA data bus.
SD15–SD0
System Data Bus is shared between ISA, 8- or 16-bit ROM/Flash memory, and PC Card
peripherals (on the ÉlanSC400 microcontroller only) and can be directly connected to all of
these devices. In addition, these signals are the upper word of the local data bus, the 32-bit
DRAM interface, and the 32-bit ROM interface. In these modes, the system data bus can be
generated via an external buffer connected to the SD bus and controlled by the buffer control
signals provided.
SPKR
TC
O
Speaker, Digital Audio Output controls an external speaker driver. It is generated from the
internal 8254-compatible timer Channel 2 output ANDed with I/O Port 0061h[1] (Speaker
Data Enable); on the ÉlanSC400 microcontroller, the PC Card speaker signals are
exclusively ORed with each other and the speaker control function of the timer to generate
the SPKR signal.
O
I
Terminal Count is driven from the DMA controller pair to indicate that the transfer count for
the currently active DMA channel has reached zero, and that the current DMA cycle is the
last transfer.
Configuration Pins
BNDSCN_EN
Boundary Scan Enable enables the boundary scan pin functions. When this pin is High, the
boundary scan interface is enabled. When this pin is Low, the boundary scan pin functions
are disabled and the pins are configured to their default functions. This pin must be held Low
during reset for normal operation.
CFG1–CFG0
I
Configuration Pins 1–0 select the data bus width for the physical device(s) selected by the
ROMCS0 pin (i.e., 8-, 16-, or 32-bit-wide). These pins are sampled at the deassertion of RESET.
CFG2
I
Configuration Pin 2 selects whether or not the system will boot from PC Card Socket A
memory card or from the device attached to ROMCS0. This pin is sampled at the deassertion
of RESET. This pin is not supported on the ÉlanSC410 microcontroller.
CFG3
I
Configuration Pin 3 enables the SD buffer control signals, DBUFOE, DBUFRDH, and
DBUFRDL. This pin is sampled at the deassertion of RESET.
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
63
AMD [ AMD ]
