Table 19. Signal Description Table (Continued)
Description
Signal
Type
LC
O
LCD Panel Line Clock is activated at the start of every pixel line. It is commonly referred to
by LCD data sheets as CL1 or CP1. This signal is not supported on the ÉlanSC410
microcontroller.
LCDD7–LCDD0
O
LCD Panel Data bits: LCDD7–LCDD0 are data bits for the LCD panel interface. When
driving 4-bit single-scan panels, bits 3–0 form a nibble-wide LCD data interface. In dual-scan
panel mode, LCDD3–LCDD0 are the data bits for the top half of the LCD, and LCDD7–
LCDD4 are the data bits for the bottom half of the LCD. When driving 8-bit single-scan panels
(monochrome or color STN), these bits are the 8-bit data interface. These signals are not
supported on the ÉlanSC410 microcontroller.
LVDD
LVEE
O
O
LCD Panel VDD Voltage Control is used to control the assertion of the LCD’s VDD voltage.
This is provided to be part of the solution in sequencing the panel’s VDD, DATA, and VEE in
the proper order during panel power-up and power-down to prevent damage to the panel
from CMOS driver latch up. VDD is used to power the LCD logic and is usually +5 V or +3 V
DC. This signal is not supported on the ÉlanSC410 microcontroller.
LCD Panel VEE Voltage Control is used to control the assertion of the LCD’s VEE voltage.
This is provided to be part of the solution in sequencing the panel’s VDD, DATA, and VEE in
the proper order during panel power-up and power-down to prevent damage to the panel
from CMOS driver latch up. VEE is the LCD contrast voltage and is either positive or negative
with an amplitude of 15–30 V DC.This signal is not supported on the ÉlanSC410
microcontroller.
M
O
O
LCD Panel AC Modulation is the AC modulation signal for the LCD. AC modulation causes
the LCD panel drivers to reverse polarity to prevent an internal DC bias from forming on the
panel. This signal is not supported on the ÉlanSC410 microcontroller.
SCK
LCD Panel Shift Clock is the nibble/byte strobe used by the LCD panel to latch a nibble or
byte of incoming data. Commonly referred to by LCD panels as CL2 or CP2. This signal is
not supported on the ÉlanSC410 microcontroller.
Boundary Scan Test Interface
BNDSCN_TCK
I
Test Clock is the boundary-scan input clock that is used to shift serial data patterns in from
BNDSCN_TDI.
BNDSCN_TDI
I
Test Data Input is the serial input stream for boundary-scan input data. This pin has a weak
internal pullup resistor. It is sampled on the rising edge of BNDSCN_TCK. If not driven, this
input is sampled High internally.
BNDSCN_TDO
BNDSCN_TMS
O
TS
Test Data Output is the serial output stream for boundary-scan result data. It is in the high-
impedance state except when scanning is in progress.
I
Test Mode Select is an input for controlling the test access port. This pin has a weak internal
pullup resistor. If it is not driven, it is sampled High internally.
Reset and Power
BBATSEN
A
Backup Battery Sense: RTC (Real Time Clock) backup battery voltage is sampled on this
pin each time the AVCC pin has power applied to it followed by a chip master reset. If this
samples below 2.4 V, the VRT bit (RTC index 0Dh) is cleared until read one time. At this time,
the VRT bit is set until BBATSEN is sampled again. BBATSEN also provides a power-on-
reset signal for the RTC when an RTC backup battery is applied for the first time.
GND
Ground Pins
RESET
I
Reset Input is an asynchronous hardware reset input equivalent to POWERGOOD in the AT
system architecture.
VCC
3.3-V DC Supply Pins provide power to the discrete logic and I/O pins.
VCC_A
Analog 3.3-V Supply Pins provide power to the analog section of the chip, including the internal
PLLs and integrated oscillator circuit. Extreme care should be taken that this supply voltage
is isolated properly to provide a clean, noise free voltage to the PLLs.
VCC_CPU
VCC_RTC
CPU
RTC
3.3-V DC Supply Pins provide power to the internal CPU.
3.3-V Supply Pin provides power to the internal real-time clock and on-board static/
configuration RAM. This pin can be driven independently of all other power pins.
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
69
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