t1
RAS
t8b
t4
t9c
t7a
t2
t6b
t6b
CASH3–CASH0
CASL3–CASL0
t3
t5
t15
t15
MA12–MA0
MWE
t24
t25
t26
t12b
t11
t12b
t10
t13
t14b
t11
D31–D0
Notes:
The EDO DRAM page hit write timing is similar to DRAM page hit write timing. See Figure 36 on page 101 for more information.
Figure 38. EDO DRAM Page Hit Read, Non-Interleaved
t1
t21
t22
RAS
t8b
t4
t2
t6b
CASH3–CASH0
CASL3–CASL0
t3
t5
t15
MA12–MA0
MWE
t24
t25
t26
t12b
t11
t10
D31–D0
Notes:
The EDO DRAM page miss write timing is similar to DRAM page miss write timing. See Figure 36 on page 101 for more
information.
Figure 39. EDO DRAM Page Miss Read, Non-Interleaved
102
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
AMD [ AMD ]
