Table 37. DRAM Cycles
33-MHz
External Bus
Symbol
Parameter Description
Notes
Unit
Min
5
Max
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
t1
t2
Row address setup time
RAS to CAS delay
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
ns
ns
ns
42.75
14.25
0
t3
Row address hold time
Column address setup time
Column address hold time
t4
t5
14.25
42.75
28.5
28.5
14.25
71.25
85.5
66.5
57
t6a
t6a
t6b
t7a
t7b
t8a
t8b
t9a
t9b
t9c
t10
t11
t12a
t12b
t13
t14a
t14b
t15
t16
t17
t18
t19
t20
t21
t22
t23
t24
t25
t26
t27
t28
t29
t30
t31
t32
t33
CAS pulse width (CPU, Fast Page mode)
CAS pulse width (graphics controller, Fast Page mode)
CAS pulse width (EDO mode)
CAS precharge (non-interleaved)
CAS precharge (interleaved)
CAS hold
CAS hold (EDO)
Fast page mode cycle time (non-interleaved)
Fast page mode cycle time (interleaved)
EDO mode cycle time
114
57
Access time from RAS
66.5
35
Access time from column address
Access time from CAS
20
Access time from CAS (EDO)
Access time from CAS precharge
Read data hold from CAS
22
40
0
Read data hold from CAS (EDO)
MA12–MA0 switching time
5
15
15
Delay between bank CAS signals
MWE setup to CAS
10
30
MWE hold from CAS
Write data setup to CAS
10
Write data hold from CAS
30
RAS precharge
60
RAS pulse width
75
RAS hold
28.5
14.25
14.25
MWE low from CAS (EDO data disable)
MWE pulse width (EDO)
Data high impedance from MWE
RAS to CAS precharge time
CAS setup time (CAS-before-RAS refresh)
CAS hold time (CAS-before-RAS refresh)
RAS pulse width during self-refresh cycle
RAS precharge time during self-refresh cycle
WE setup time (CAS-before-RAS refresh)
WE hold time (CAS-before-RAS refresh)
15
15
10
25
100
130
25
25
Notes:
1. All timings assume 70-ns DRAMs, fastest programmable timing, and a 66-MHz clock for the memory controller.
98
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
AMD [ AMD ]
