Table 38. ISA Cycles (Continued)
33-MHz
External Bus
Symbol
Parameter Description
Notes
Unit
Min
53
Max
t29
t30
t31
t32a
t32b
t33a
t33b
t34
t35
t36
t37
t38
t39
t41
t42
t43
t44
t45
t46
t47
t48
t49
t50
t51
t52
t53
t54
t55
t56
Hold, SA, SBHE from read command
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Setup, TC to read command deassertion
Hold, TC from read command deassertion
Pulse width, I/O write command
470
60
400
700
800
470
Pulse width, I/O read command
Pulse width, memory read command
Pulse width, memory write command
Delay, MEMR to valid data
272
241
Hold, SD from MEMR deassertion
11
Delay, IOR to valid data
Hold, SD from IOR deassertion
11
-21
-214
45
30
0
Setup, SD to MEMW assertion
Setup, SD to IOW assertion
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Setup, DBUFRDL/DBUFRDH to write command Low
Hold, DBUFRDL/DBUFRDH from write command High
Setup, DBUFRDL/DBUFRDH to read command Low
Hold, DBUFRDL/DBUFRDH from read command High
Setup, DBUFOE Low to write command Low
Hold, DBUFOE from write command High
Setup, DBUFOE Low to read command Low
Hold, DBUFOE from read command High
Setup, DBUFRDL/DBUFRDH to mem read command Low, DMA
Hold, DBUFRDL/DBUFRDH from mem read command High, DMA
Setup, DBUFOE Low to mem read command Low, DMA
Hold, DBUFOE from mem read command High, DMA
Setup, DBUFRDL/DBUFRDH to I/O read command Low, DMA
Setup, DBUFOE Low to I/O read command Low, DMA
Hold, DBUFOE from I/O read command High, DMA
Hold, DBUFRDL/DBUFRDH from I/O read command High, DMA
10
45
30
0
10
0
10
0
10
0
0
10
10
Notes:
1. These parameters are applicable only when an external data transceiver is used to isolate the SD bus.
106
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
AMD [ AMD ]
