t27
t7a
t28
t29
CASH3–CASH0
CASL3–CASL0
t33
t33
t33
t33
t32
t22
t22
t22
t22
RAS0
RAS1
RAS2
RAS3
MWE
Notes:
The diagram above shows RAS and CAS behavior for an ÉlanSC400 or ÉlanSC410 microcontroller running at a frequency of
16 MHz or less. In this case, the RAS signals are not staggered and all are driven (Low) at the same time to consume less DRAM
bandwidth for refresh activity (consumed due to a slower clock frequency).
Figure 42. DRAM Slow Refresh
104
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet