clk_mem
t27
t27
t29
t29
t7a
t27
t27
t27
t27
t28
t27
t27
t7a
t28
t28
t28
t29
t29
CASH3–CASH0
CASL3–CASL0
t33
t32
t22
RAS0
t33
t32
t22
RAS1
RAS2
t33
t32
t22
t33
t32
t22
RAS3
MWE
Figure 40. DRAM CAS-Before-RAS Refresh
t7a
t27
t27
t28
7a
CASH3–CASH0
SS
CASL3–CASL0
t21
t30
SS
t31
RAS
MWE
Notes:
Because the sequence shown above is performed when the microcontroller is in Suspend mode, the DRAMs must self-refresh.
The RAS and CAS signals are held active (Low) for the entire time that the microcontroller is in Suspend mode. The timing
diagram also shows a following cycle that brings RAS and CAS High again. The Low period of RAS and CAS can be of a long
duration.
Figure 41. DRAM Self-Refresh
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
103
AMD [ AMD ]
