Table 38. ISA Cycles
33-MHz
External Bus
Symbol
Parameter Description
Notes
Unit
Min
Max
t1a
Setup, SA, SBHE stable to command assertion, 16-bit I/O,
8-bit I/O, Mem
120
ns
t1b
t2a
t2b
t3a
t3b
t3c
t3d
t3e
t3f
Setup, SA, SBHE stable to command assertion, 16-bit Mem
Delay, MCS16 stable from SA
120
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
102
122
Delay, IOCS16 stable from SA
Pulse width, IOW, 8-bit cycle
530
530
530
530
165
240
165
240
53
Pulse width, MEMW, 8-bit cycle
Pulse width, IOR, 8-bit cycle
Pulse width, MEMR, 8-bit cycle
Pulse width, IOW, 16-bit cycle
Pulse width, MEMW, 16-bit cycle
t3g
t3h
t4
Pulse width, IOR, 16-bit cycle
Pulse width, MEMR, 16-bit cycle
SA, SBHE hold from command deassertion
IOCHRDY delay from IOR, MEMR, IOW, MEMW (8-bit)
IOCHRDY delay from IOR, MEMR, IOW, MEMW (16-bit)
IOR, MEMR, IOW, MEMW delay from IOCHRDY
IOR, MEMR, IOW, MEMW high time (8-bit)
IOR, MEMR, IOW, MEMW high time (16-bit)
Delay, BALE rising from IOR, MEMR, IOW, MEMW deassertion
IOCHRDY pulse width
t5a
t5b
t6
378
66
125
187
125
46
t7a
t7b
t8
t9
120 ns 15.6µs
t11a
Setup, SD to write command assertion, 8-bit memory, I/O write and
16-bit I/O write
33
ns
t11b
t12
Setup, SD to write command assertion, 16-bit memory write
Hold, SD from write command deassertion
Data access time, 8-bit read
-29
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t13a
t13b
t13c
t14
489
132
209
0
Data access time, 16-bit I/O read
Data access time, 16-bit memory read
Hold, SD from read command deassertion
Setup, SA, SBHE stable to BALE falling edge
Pulse width, BALE
t15
61
t16
60
t17
Setup, AEN high to IOR/IOW assertion
Setup, SA, SBHE stable to command assertion
Hold, DRQ from DACK assertion
145
102
0
t19
t20
t21
Setup, DACK assertion to I/O command assertion
Setup, IOR assertion to MEMW command
Setup, MEMR command assertion to IOW command
Delay, IOCHRDY assertion to command high
Delay, memory command to IOCHRDY deassertion
Hold, command off to DACK off
145
235
0
t22a
t22b
t23
200
125
60
t24
t25
t26
Hold, read command off from write command off
Hold, AEN from command off
50
t27
60
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
105
AMD [ AMD ]
