Basic Non-Burst Write Transfer
Basic Burst Write Transfer
By default, the Am79C978 controller uses non-burst
cycles in all bus master write operations. All controller
non-burst write accesses are of the PCI command type
Memory Write (type 7). The byte enable signals indi-
cate the byte lanes that have valid data. The
Am79C978 controller typically performs more than one
non-burst write transaction within a single bus master-
ship period. FRAME is dropped between consecutive
non-burst write cycles. REQ stays asserted until
FRAME is asserted for the last transaction. The
Am79C978 controller supports zero wait state write cy-
cles except with descriptor write transfers. (See the
section Descriptor DMA Transfers for the only excep-
tion.) It asserts IRDY immediately after the address
phase.
The Am79C978 controller supports burst mode for all
bus master write operations. The burst mode must be
enabled by setting BWRITE (BCR18, bit 5). To allow
burst transfers in descriptor write operations, the
Am79C978 controller must also be programmed to use
SWSTYLE 3 (BCR20, bits 7-0). All controller burst
write transfers are of the PCI command type Memory
Write (type 7). AD[1:0] will both be 0 during the address
phase indicating a linear burst order. The byte enable
signals indicate the byte lanes that have valid data.
The Am79C978 controller will always perform a single
burst write transaction per bus mastership period,
where transaction is defined as one address phase and
one or multiple data phases. The Am79C978 controller
supports zero wait state write cycles except with the
case of descriptor write transfers. (See the section De-
scriptor DMA Transfers for the only exception.) The de-
vice asserts IRDY immediately after the address phase
and at the same time starts sampling DEVSEL.
FRAME is deasserted when the next to last data phase
is completed.
Figure 16 shows two non-burst write transactions. The
first transaction has two wait states. The target inserts
one wait state by asserting DEVSEL one clock late and
another wait state by also asserting TRDY one clock
late. The second transaction shows a zero wait state
write cycle. The target asserts DEVSEL and TRDY in
the same cycle as the Am79C978 controller asserts
IRDY.
CLK
1
2
3
4
5
6
7
8
9
10
FRAME
DATA
ADDR
0111
ADDR DATA
AD
BE
0111
BE
C/BE
PAR
PAR
PAR
PAR
PAR
IRDY
TRDY
DEVSEL
REQ
GNT
22206B-19
DEVSEL is sampled
Figure 16. Non-Burst Write Transfer
Figure 17 shows a typical burst write access. The
Am79C978 controller arbitrates for the bus, is granted
access, and writes four 32-bit words (DWords) to the
system memory and then releases the bus. In this ex-
Am79C978
45
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