CLK
1
2
3
4
5
6
7
8
9
10
FRAME
DATA
ADDR
CMD
AD
C/BE
BE
PAR
PAR
PAR
PERR
IRDY
TRDY
DEVSEL
22206B-15
Figure 12. Slave Cycle Data Parity Error Response
Master Bus Interface Unit
Table 7. Master Commands (Continued)
The master Bus Interface Unit (BIU) controls the acqui-
sition of the PCI bus and all accesses to the initializa-
tion block, descriptor rings, and the receive and
transmit buffer memory. Table 7 shows the usage of
PCI commands by the Am79C978 controller in master
mode.
1010
Configuration Read Not used
Configuration Write Not used
1011
1100
1101
1110
Memory Read
Multiple
Read of the transmit
buffer in burst mode
Dual Address Cycle Not used
Read of the transmit
buffer in burst mode
Memory Read Line
Table 7. Master Commands
Memory Write
Invalidate
C[3:0]
0000
Command
Interrupt
Acknowledge
Special Cycle
I/O Read
Use
1111
Not used
Not used
Bus Acquisition
0001
0010
0011
0100
0101
Not used
Not used
Not used
The microcode will determine when a DMA transfer
should be initiated. The first step in any bus master
transfer is to acquire ownership of the bus. This task is
handled by synchronous logic within the BIU. Bus own-
ership is requested with the REQ signal and ownership
is granted by the arbiter through the GNT signal.
I/O Write
Reserved
Reserved
Read of the initialization
block and descriptor
rings
Read of the transmit
buffer in non-burst mode
Figure 13 shows the Am79C978 controller bus acquisi-
tion. REQ is asserted and the arbiter returns GNT while
another bus master is transferring data. The
Am79C978 controller waits until the bus is idle
(FRAME and IRDY deasserted) before it starts driving
AD[31:0] and C/BE[3:0] on clock 5. FRAME is asserted
at clock 5 indicating a valid address and command on
AD[31:0] and C/BE[3:0]. The Am79C978 controller
does not use address stepping which is reflected by
0110
Memory Read
Write to the descriptor
rings and to the receive
buffer
0111
Memory Write
1000
1001
Reserved
Reserved
42
Am79C978
AMD [ AMD ]
