CLK
CLK
1
2
3
4
5
6
1
2
3
4
5
FRAME
FRAME
AD
C/BE
PAR
1st DATA
DATA
AD
C/BE
PAR
ADDR
CMD
1st DATA
BE
BE
BE
PAR
PAR
PAR
PAR
IRDY
TRDY
SERR
DEVSEL
DEVSEL
STOP
22206B-14
Figure 11. Address Parity Error Response
22206B-13
During the data phase of an I/O write, memory-mapped
I/O write, or configuration write command that selects
the Am79C978 controller as target, the device samples
the AD[31:0] and C/BE[3:0] lines for parity on the clock
edge, and data is transferred as indicated by the asser-
tion of IRDY and TRDY. PAR is sampled in the follow-
ing clock cycle. If a parity error is detected and
reporting of that error is enabled by setting PERREN
(PCI Command register, bit 6) to 1, PERR is asserted
one clock later. The parity error will always set PERR
(PCI Status register, bit 15) to 1 even when PERREN
is cleared to 0. The Am79C978 controller will finish a
transaction that has a data parity error in the normal
way by asserting TRDY. The corrupted data will be writ-
ten to the addressed location.
Figure 10. Disconnect of Slave Burst Transfer -
Host Inserts Wait States
Parity Error Response
When the Am79C978 controller is not the current bus
master, it samples the AD[31:0], C/BE[3:0], and the
PAR lines during the address phase of any PCI com-
mand for a parity error. When it detects an address par-
ity error, the Am79C978 controller sets PERR (PCI
Status register, bit 15) to 1. When reporting of that error
is enabled by setting SERREN (PCI Command regis-
ter, bit 8) and PERREN (PCI Command register, bit 6)
to 1, the Am79C978 controller also drives the SERR
signal low for one clock cycle and sets SERR (PCI Sta-
tus register, bit 14) to 1. The assertion of SERR follows
the address phase by two clock cycles. The
Am79C978 controller will not assert DEVSEL for a PCI
transaction that has an address parity error when PER-
REN and SERREN are set to 1. See Figure 11.
Figure 12 shows a transaction that suffered a parity
error at the time data was transferred (clock 7, IRDY
and TRDY are both asserted). PERR is driven high at
the beginning of the data phase and then drops low due
to the parity error on clock 9, two clock cycles after the
data was transferred. After PERR is driven low, the
Am79C978 controller drives PERR high for one clock
cycle, since PERR is a sustained tri-state signal.
Am79C978
41
AMD [ AMD ]
