ADSTEP (bit 7) in the PCI Command register being
hardwired to 0.
Am79C978 controller will internally discard unneeded
bytes.
The Am79C978 controller typically performs more than
one non-burst read transaction within a single bus
mastership period. FRAME is dropped between con-
secutive non-burst read cycles. REQ stays asserted
until FRAME is asserted for the last transaction. The
Am79C978 controller supports zero wait state read cy-
cles. It asserts IRDY immediately after the address
phase and at the same time starts sampling DEVSEL.
Figure 14 shows two non-burst read transactions. The
first transaction has zero wait states. In the second
transaction, the target extends the cycle by asserting
TRDY one clock later.
CLK
1
2
3
4
5
FRAME
ADDR
CMD
AD
C/BE
Basic Burst Read Transfer
IRDY
REQ
The Am79C978 controller supports burst mode for all
bus master read operations. The burst mode must be
enabled by setting BREADE (BCR18, bit 6). To allow
burst transfers in descriptor read operations, the
Am79C978 controller must also be programmed to use
SWSTYLE 3 (BCR20, bits 7-0). All burst read accesses
to the initialization block and descriptor ring are of the
PCI command type Memory Read (type 6). Burst read
accesses to the transmit buffer typically are longer than
two data phases. When MEMCMD (BCR18, bit 9) is
cleared to 0, all burst read accesses to the transmit
buffer are of the PCI command type Memory Read Line
(type 14). When MEMCMD (BCR18, bit 9) is set to 1,
all burst read accesses to the transmit buffer are of the
PCI command type Memory Read Multiple (type 12).
AD[1:0] will both be 0 during the address phase indicat-
ing a linear burst order. Note that during a burst read
operation, all byte lanes will always be active. The
Am79C978 controller will internally discard unneeded
bytes.
GNT
22206B-16
Figure 13. Bus Acquisition
In burst mode, the deassertion of REQ depends on the
setting of EXTREQ (BCR18, bit 8). If EXTREQ is
cleared to 0, REQ is deasserted at the same time as
FRAME is asserted. (The Am79C978 controller never
performs more than one burst transaction within a sin-
gle bus mastership period.) If EXTREQ is set to 1, the
Am79C978 controller does not deassert REQ until it
starts the last data phase of the transaction.
Once asserted, REQ remains active until GNT has be-
come active and independent of subsequent setting of
STOP (CSR0, bit 2) or SPND (CSR5, bit 0). The asser-
tion of H_RESET or S_RESET, however, will cause
REQ to go inactive immediately.
The Am79C978 controller will always perform only a
single burst read transaction per bus mastership pe-
riod, where transaction is defined as one address
phase and one or multiple data phases. The
Am79C978 controller supports zero wait state read cy-
cles. It asserts IRDY immediately after the address
phase and at the same time starts sampling DEVSEL.
FRAME is deasserted when the next to last data phase
is completed.
Bus Master DMA Transfers
There are four primary types of DMA transfers. The
Am79C978 controller uses non-burst as well as burst
cycles for read and write access to the main memory.
Figure 15 shows a typical burst read access. The
Am79C978 controller arbitrates for the bus, is granted
access, reads three 32-bit words (DWord) from the sys-
tem memory, and then releases the bus. In the exam-
ple, the memory system extends the data phase of
each access by one wait state. The example assumes
that EXTREQ (BCR18, bit 8) is cleared to 0, therefore,
REQ is deasserted in the same cycle as FRAME is as-
serted.
Basic Non-Burst Read Transfer
By default, the Am79C978 controller uses non-burst
cycles in all bus master read operations. All controller
non-burst read accesses are of the PCI command type
Memory Read (type 6). Note that during a non-burst
read operation, all byte lanes will always be active. The
Am79C978
43
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