CLK
2
3
4
5
6
7
8
9
1
11
10
FRAME
ADDR +8
i
ADDR
0111
DATA
DATA
AD
C/BE
PAR
i
0000
0111
PAR
PAR
IRDY
TRDY
DEVSEL
STOP
REQ
GNT
22206B-21
DEVSEL is sampled
Figure 18. Disconnect With Data Transfer
Disconnect Without Data Transfer
about the success of the previous data transfers in the
current transaction. The Am79C978 controller termi-
nates the current transfer with the deassertion of
FRAME on clock 5 and of IRDY one clock cycle later.
It finally releases the bus on clock 6.
Figure 19 shows a target disconnect sequence during
which no data is transferred. STOP is asserted on clock
4 without TRDY being asserted at the same time. The
Am79C978 controller terminates the access with the
deassertion of FRAME on clock 5 and of IRDY one
clock cycle later. It finally releases the bus on clock 7.
The Am79C978 controller will again request the bus
after two clock cycles to retry the last transfer. The
starting address of the new transfer will be the address
of the last non-transferred data.
Since data integrity is not guaranteed, the Am79C978
controller cannot recover from a target abort event.
TheAm79C978 controller will reset all CSR locations to
their STOP_RESET values. The BCR and PCI config-
uration registers will not be cleared. Any on-going net-
work transmission is terminated in an orderly
sequence. If less than 512 bits have been transmitted
onto the network, the transmission will be terminated
immediately, generating a runt packet. If 512 bits or
more have been transmitted, the message will have the
current FCS inverted and appended at the next byte
boundary to guarantee an FCS error is detected at the
receiving station.
Target Abort
Figure 20 shows a target abort sequence. The target
asserts DEVSEL for one clock. It then deasserts
DEVSEL and asserts STOP on clock 4. A target can
use the target abort sequence to indicate that it can-
not service the data transfer and that it does not want
the transaction to be retried. Additionally, the
Am79C978 controller cannot make any assumption
Am79C978
47
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