This bit is always read/write ac-
cessible. XPHYRST is set to 0 by
H_RESET and is unaffected by
S_RESET and the STOP bit.
XPHYRST is only valid when the
internal Network Port Manager is
scanning for a network port.
es the transmit frame. TX_ER is
looped back as RX_ER. Howev-
er, TX_ER will not get asserted
by the Am79C978 controller to
signal an error. The TX_ER func-
tion is reserved for future use.
This bit is always read/write ac-
cessible. MIIILP is set to 0 by
H_RESET and is unaffected by
S_RESET and the STOP bit.
5
XPHYANE PHY Auto-Negotiation Enable.
This bit will force the PHY into en-
abling Auto-Negotiation. When
set to 0 the Am79C978 controller
will send a management frame
disabling Auto-Negotiation.
0
RES
Reserved location. Written as
zero and read as undefined.
BCR33: PHY Address Register
This bit is always read/write ac-
cessible. XPHYANE is set to 0 by
H_RESET and is unaffected by
S_RESET and the STOP bit.
XPHYANE is only valid when the
internal Network Port Manager is
scanning for a network port.
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15
SHADOW
If the user wishes to update the
contents of the BCR33 shadow
register, setting the MSB of the
value written into BCR33 (bit 15)
will enable the contents to be si-
multaneously written to BCR33
shadow.
4
XPHYFD
PHY Full Duplex. When set, this
bit will force the PHY into full du-
plex when Auto-Negotiation is not
enabled.
This bit is always read/write ac-
cessible. XPHYFD is set to 0 by
H_RESET, and is unaffected by
S_RESET and the STOP bit.
14
13
MII_SEL
MII selected. This bit indicates
whether the internal PHY is se-
lected.
3
XPHYSP
PHY Speed. When set, this bit
will force the PHY into 100 Mbps
mode when Auto-Negotiation is
not enabled.
AUTONEG_COMPLETE
Internal Auto-Negotiation com-
plete. Valid for internal PHY only.
This bit is always read/write ac-
cessible. XPHYSP is set to 0 by
H_RESET, and is unaffected by
S_RESET and the STOP bit.
12
11
LINK STATUS
Link Status. This bit is a valid link
status indication.
FULL_DUPLEX
2
1
RES
Reserved location. Written as
zero and read as undefined.
Full Duplex. This bit indicates that
the MAC is configured for Full-
Duplex operation.
MIIILP
Media Independent Interface In-
ternal Loopback. When set, this
bit will cause the internal portion
of the MII data port to loopback
on itself. The interface is mapped
in the following way. The
TXD[3:0] nibble data path is
looped back onto the RXD[3:0]
nibble data path. TX_CLK is
looped back as RX_CLK. TX_EN
is looped back as RX_DV. CRS is
correctly OR’d with TX_EN and
RX_DV and always encompass-
10
SPEED_SEL Speed Selected. This bit indi-
cates if High or Low speed has
been selected by MAC.
9-5
PHYAD
Management Frame PHY Ad-
dress. PHYAD contains the 5-bit
PHY Address field that is used in
the management frame that gets
clocked out via the MII manage-
ment port pins (MDC and MDIO)
170
Am79C978
AMD [ AMD ]
