any byte write accesses to the
SRAM, the user will have to fol-
Port Lower Address (EPADDRL)
will roll over to 0000h. When the
LAAINC bit is set to 0, the Expan-
sion Port Lower Address will not
be affected in any way after an
access to EBDATA (BCR30) and
must be programmed.
low
the
read-modify-write
scheme. On any byte read ac-
cesses to the SRAM, the user will
have to chose which byte is
needed from the complete word
returned in BCR30.
This bit is always read accessi-
ble; write accessible only when
the STOP bit is set. LAINC is 0 af-
ter H_RESET and is unaffected
by S_RESET or the STOP bit.
Flash accesses are started when
a read or write is performed on
BCR30 and the FLASH (BCR 29,
bit 15) is set to 1. During Flash
accesses all bits in EPADDR are
valid.
13-4 RES
Reserved locations. Written as
zeros and read as undefined.
Read accessible always; write
accessible only when the STOP
is set or when SRAM SIZE
(BCR25, bits 7-0) is 0. EPADDRL
is undefined after H_RESET and
is unaffected by S_RESET or
STOP.
3-0
EPADDRU Expansion Port Address Upper.
This upper portion of the Expan-
sion Bus address is used to pro-
vide addresses for Flash/EPROM
port accesses.
This bit is always read accessi-
ble; write accessible only when
the STOP bit is set or when
SRAM SIZE (BCR25, bits 7-0) is
0. EPADDRU is undefined after
H_RESET and is unaffected by
S_RESET or the STOP bit.
BCR29: Expansion Port Address Upper (Used for
Flash/EPROM Accesses)
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
BCR30: Expansion Bus Data Port Register
15
FLASH
Flash Access. When the FLASH
bit is set to 1, the Expansion Bus
access will be a Flash cycle.
When FLASH is set to 0, the Ex-
pansion Bus access will be a
SRAM cycle. For a complete de-
scription, see the section on Ex-
pansion Bus Accesses. This bit is
only applicable to reads or writes
to EBDATA (BCR30). It does not
affect Expansion ROM accesses
from the PCI system bus.
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0 EBDATA
Expansion Bus Data Port. EBDA-
TA is the data port for operations
on the Expansion Port accesses
involving SRAM and Flash ac-
cesses. The type of access is set
by the FLASH bit (BCR 29, bit
15). When the FLASH bit is set to
1, the Expansion Bus access will
follow the Flash access timing.
When the FLASH bit is set to 0,
the Expansion Bus access will
follow the SRAM access timing.
This bit is always read accessi-
ble; write accessible only when
the STOP bit is set. FLASH is 0
after H_RESET and is unaffected
by S_RESET or the STOP bit.
Note: It is important to set the
FLASH bit and load Expansion
Port Address EPADDR (BCR28,
BCR29) with the required ad-
dress before attempting read or
write to the Expansion Bus data
port. The Flash and SRAM ac-
cesses use different address
14
LAAINC
Lower Address Auto Increment.
When the LAAINC bit is set to 1,
the Expansion Port Lower Ad-
dress will automatically increment
by one after a read or write ac-
cess to EBDATA (BCR30). When
EBADDRL reaches FFFFh and
LAAINC is set to 1, the Expansion
Am79C978
167
AMD [ AMD ]
