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AM79C978KC/W 参数 Datasheet PDF下载

AM79C978KC/W图片预览
型号: AM79C978KC/W
PDF下载: 下载PDF文件 查看货源
内容描述: 单芯片1/10 Mbps的PCI家庭网络控制器 [Single-Chip 1/10 Mbps PCI Home Networking Controller]
分类和应用: 控制器PC
文件页数/大小: 261 页 / 3499 K
品牌: AMD [ AMD ]
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phases. Incorrect configuration  
will result in a possible corruption  
of data.  
The STVAL value is interpreted  
as an unsigned number with a  
resolution of 256 Time Base  
Clock periods. For instance, a  
value of 122 ms would be pro-  
grammed with a value of 9531  
(253Bh) if the Time Base Clock is  
running at 20 MHz. A value of 0 is  
undefined and will result in erratic  
behavior.  
Flash read cycles are performed  
when BCR30 is read and the  
FLASH bit (BCR29, bit 15) is set  
to 1. Upon completion of the read  
cycle, the 8-bit result for Flash ac-  
cess is stored in EBDATA[7:0],  
EBDATA[15:8] is undefined.  
Flash write cycles are performed  
when BCR30 is written and the  
FLASH bit (BCR29, bit 15) is set  
to 1. EBDATA[7:0] only is valid  
for write cycles.  
Read and write accessible al-  
ways. STVAL is set to FFFFh af-  
ter H_RESET and is unaffected  
by S_RESET and the STOP bit.  
SRAM read cycles are performed  
when BCR30 is read and the  
FLASH bit (BCR29, bit 15) is set  
to 0. Upon completion of the read  
cycle, the 16-bit result for SRAM  
access is stored in EBDATA.  
Write cycles to the SRAM are in-  
voked when BCR30 is written  
and the FLASH bit (BCR29, bit  
15) is set to 0. Byte writes to the  
SRAM must use a read-modify-  
write scheme since the word is al-  
ways valid for SRAM write or  
read accesses.  
BCR32: PHY Control and Status Register  
Note: Bits 15-0 in this register are programmable  
through the EEPROM.  
Bit  
Name  
Description  
31-16 RES  
Reserved locations. Written as  
zeros and read as undefined.  
15  
ANTST  
Reserved for manufacturing  
tests. Written as 0 and read as  
undefined.  
Note: Use of this bit will cause  
data corruption and erroneous  
operation.  
This bit is read and write accessi-  
ble only when the STOP is set or  
when SRAM SIZE (BCR25, bits  
7-0) is 0. EBDATA is undefined  
after H_RESET and is unaffected  
by S_RESET and the STOP bit.  
This bit is always read/write ac-  
cessible. ANTST is set to 0 by  
H_RESET and is unaffected by  
S_RESET and the STOP bit.  
BCR31: Software Timer Register  
14  
MIIPD  
MII PHY Detect (is used for man-  
ufacturing tests). MIIPD reflects  
the quiescent state of the MDIO  
pin. MIIPD is continuously updat-  
ed whenever there is no manage-  
ment operation in progress on the  
MII interface. When a manage-  
ment operation begins on the in-  
terface, the state of MIIPD is  
preserved until the operation  
ends, when the quiescent state is  
again monitored and continuous-  
ly updates the MIIPD bit. When  
the MDIO pin is at a quiescent  
LOW state, MIIPD is cleared to 0.  
When the MDIO pin is at a quies-  
cent HIGH state, MIIPD is set to  
1. MIIPD is used by the automatic  
port selection logic to select the  
Bit  
Name  
Description  
31-16 RES  
Reserved locations. Written as  
zeros and read as undefined.  
15-0 STVAL  
Software Timer Value. STVAL  
controls the maximum time for  
the Software Timer to count be-  
fore generating the STINT  
(CSR7, bit 11) interrupt. The Soft-  
ware Timer is a free-running timer  
that is started upon the first write  
to STVAL. After the first write, the  
Software Timer will continually  
count and set the STINT interrupt  
at the STVAL period.  
168  
Am79C978