boundary where the receive buffer
begins in the SRAM. The transmit
buffer in the SRAM begins at ad-
dress 0 and ends at the address
located just before the address
specified by SRAM_BND. There-
fore, the receive buffer always be-
gins on a 512 byte boundary. The
lower bits are assumed to be ze-
ros. SRAM_BND has no effect in
the Low Latency Receive mode.
14
LOLATRX Low Latency Receive. When the
LOLATRX bit is set to 1, the
Am79C978 controller will switch
to an architecture applicable to
cut-through
switches.
The
Am79C978 controller will assert a
receive frame DMA after only 16
bytes of the current receive frame
has been received regardless of
where the RCVFW (CSR80, bits
13-12) are set. The watermark is
a fixed value and cannot be
changed. The receive FIFOs will
be in NO_SRAM mode while all
transmit traffic is buffered through
the SRAM. This bit is only valid
and the low latency receive only
enabled when the SRAM_SIZE
(BCR25, bits 7-0) bits are non-ze-
ro. SRAM_BND (BCR26, bits 7-
0) has no meaning when the
Am79C978 controller is in the
Low Latency mode. See the sec-
tion on SRAM Configuration for
more details.
Note: The minimum allowed
number of pages is four. The
Am79C978 controller will not op-
erate correctly with less than four
pages of memory per queue. See
Table 41 for SRAM_BND pro-
gramming details.
Table 41. SRAM_BND Programming
SRAM Addresses
SRAM_BND [7:0]
Minimum SRAM_BND
Address
04h
13h
Maximum SRAM_BND Address
When the LOLATRX bit is set to
0, the Am79C978 controller will
return to a normal receive config-
uration. The runt packet accept
bit (RPA, CSR124, bit 3) must be
set when LOLATRX is set.
CAUTION:
Programming
SRAM_BND and SRAM_SIZE
to the same value will cause
data corruption except in the
case where SRAM SIZE is 0.
CAUTION: To provide data in-
tegrity when switching into
and out of the low latency
mode, DO NOT SET the
FASTSPNDE (CSR7, bit 15) bit
when setting the SPND bit. Re-
ceive frames WILL be overwrit-
Read accessible always; write
accessible only when the STOP
bit is set. SRAM_BND is set to
00000000b during H_RESET
and is unaffected by S_RESET or
STOP.
ten
and
the
Am79C978
BCR27: SRAM Interface Control Register
controller may give erratic be-
havior when it is enable again.
The minimum allowed number
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
of pages
is four.
The
Am79C978 controller will not
operate correctly in the LOLA-
TRX mode with less than four
pages of memory.
15
PTR TST
Reserved. Reserved for manu-
facturing tests. Written as zero
and read as undefined.
Read/Write accessible only when
the STOP bit is set. LOLATRX is
cleared to 0 after H_RESET or
S_RESET and is unaffected by
STOP.
Note: Use of this bit will cause
data corruption and erroneous
operation.
This bit is always read/write ac-
cessible. PTR_TST is set to 0 by
H_RESET and is unaffected by
S_RESET and the STOP bit.
13-6 RES
Reserved locations. Written as
zeros and read as undefined.
Am79C978
165
AMD [ AMD ]
