31-0 RES
15-0 SVID
Reserved locations. Written as
zeros and read as undefined.
Note: Bits 7-0 in this register are programmable
through the EEPROM.
31-8 RES
Reserved locations. Written as
zeros and read as undefined.
Subsystem Vendor ID. SVID is
used together with SID (BCR24,
bits 15-0) to uniquely identify the
add-in board or subsystem the
Am79C978 controller is used in.
Subsystem Vendor IDs can be
obtained from the PCI SIG. A val-
ue of 0 (the default) indicates that
the Am79C978 controller does
not support subsystem identifica-
tion. SVID is aliased to the PCI
Configuration Space register
Subsystem Vendor ID (offset
2Ch).
7-0 SRAM_SIZE SRAM Size. Specifies the upper
8 bits of the 16-bit total size of the
SRAM buffer. Each bit in
SRAM_SIZE accounts for a 512-
byte page. The starting address
for the lower 8 bits is assumed to
be 00h and the ending address
for the lower is assumed to be
FFh. Therefore, the maximum ad-
dress range is the starting ad-
dress of 0000h to ending address
of ((SRAM_SIZE+1) * 256 words)
or 17FFh. An SRAM_SIZE value
of all zeros specifies that no
SRAM will be used and the inter-
nal FIFOs will be joined into a
contiguous FIFO similar to the
PCnet-PCI II controller.
This bit is always read accessi-
ble. SVID is read only. Write op-
erations are ignored. SVID is
cleared to 0 by H_RESET and is
not affected by S_RESET or by
setting the STOP bit.
Note: The minimum allowed
number of pages is eight for nor-
mal network operation. The
Am79C978 controller will not op-
erate correctly with less than the
eight pages of memory. When
the minimum number of pages is
used, these pages must be allo-
cated four each for transmit and
receive.
BCR24: PCI Subsystem ID Register
Note: Bits 15-0 in this register are programmable
through the EEPROM.
Bit
Name
Description
31-16 RES
15-0 SID
Reserved locations. Written as
zeros and read as undefined.
Subsystem ID. SID is used to-
gether with SVID (BCR23, bits
15-0) to uniquely identify the add-
in board or subsystem the
Am79C978 controller is used in.
The value of SID is up to the sys-
tem vendor. A value of 0 (the de-
CAUTION:
Programming
SRAM_BND and SRAM_SIZE
to the same value will cause
data corruption except in the
case where SRAM_SIZE is 0.
fault)
indicates
that
the
This bit is always read accessi-
ble; write accessible only when
the STOP bit is set. SRAM_SIZE
is set to 000000b during
H_RESET and is unaffected by
S_RESET or STOP.
Am79C978 controller does not
support subsystem identification.
SID is aliased to the PCI configu-
ration space register Subsystem
ID (offset 2Eh).
This bit is always read accessi-
ble. SID is read only. Write oper-
ations are ignored. SID is cleared
to 0 by H_RESET and is not af-
fected by S_RESET or by setting
the STOP bit.
BCR26: SRAM Boundary Register
Bit Name Description
Note: Bits 7-0 in this register are programmable
through the EEPROM.
31-8 RES
Reserved locations. Written as
zeros and read as undefined.
BCR25: SRAM Size Register
Bit
Name
Description
7-0 SRAM_BND SRAM Boundary. Specifies the
upper 8 bits of the 16-bit address
164
Am79C978
AMD [ AMD ]
