10
APERREN Advanced Parity Error Handling
Enable. When APERREN is set
to 1, the BPE bits (RMD1 and
TMD1, bit 23) start having a
meaning. BPE will be set in the
descriptor associated with the
buffer that was accessed when a
data parity error occurred. Note
that since the advanced parity er-
ror handling uses an additional bit
in the descriptor, SWSTYLE (bits
7-0 of this register) must be set to
2 or 3 to program the Am79C978
controller to use 32-bit software
structures.
faults to 0) and is not affected by
S_RESET or STOP.
If SSIZE32 is reset, then bits
IADR[31:24] of CSR2 will be
used to generate values for the
upper 8 bits of the 32-bit address
bus during master accesses initi-
ated by the Am79C978 controller.
This action is required, since the
16-bit software structures speci-
fied by the SSIZE32 = 0 setting
will yield only 24 bits of address
for Am79C978 controller bus
master accesses.
If SSIZE32 is set, then the soft-
ware structures that are common
to the Am79C978 controller and
the host system will supply a full
32 bits for each address pointer
that is needed by the Am79C978
controller for performing master
accesses.
APERREN does not affect the re-
porting of address parity errors or
data parity errors that occur when
the Am79C978 controller is the
target of the transfer.
Read anytime; write accessible
only when either the STOP or the
SPND bit is set. APERREN is
cleared by H_RESET and is not
affected by S_RESET or STOP.
The value of the SSIZE32 bit has
no effect on the drive of the upper
8 address bits. The upper 8 ad-
dress pins are always driven, re-
gardless of the state of the
SSIZE32 bit.
9
8
RES
Reserved location. Written as ze-
ro; read as undefined.
SSIZE32
Software Size 32 bits. When set,
this bit indicates that the
Am79C978 controller utilizes 32-
bit software structures for the ini-
tialization block and the transmit
and receive descriptor entries.
When cleared, this bit indicates
that the Am79C978 controller uti-
lizes 16-bit software structures for
the initialization block and the
transmit and receive descriptor
entries. In this mode, the
Am79C978 controller is back-
wards compatible with the
Am7990 LANCE and Am79C960
PCnet-ISA controllers.
Note that the setting of the
SSIZE32 bit has no effect on the
defined width for I/O resources.
I/O resource width is determined
by the state of the DWIO bit
(BCR18, bit 7).
7-0
SWSTYLE Software Style register. The val-
ue in this register determines the
style of register and memory re-
sources that shall be used by the
Am79C978 controller. The Soft-
ware Style selection will affect the
interpretation of a few bits within
the CSR space, the order of the
descriptor entries and the width of
the descriptors and initialization
block entries.
The value of SSIZE32 is deter-
mined by the Am79C978 control-
ler according to the setting of the
Software Style (SWSTYLE, bits
7-0 of this register).
All Am79C978 CSR bits and all
descriptor, buffer, and initializa-
tion block entries not cited in the
Table 40 are unaffected by the
Software Style selection and are,
therefore, always fully functional
as specified in the CSR and BCR
sections.
This bit is always read accessi-
ble. SSIZE32 is read only; write
operations will be ignored.
SSIZE32 will be cleared after
H_RESET (since SWSTYLE de-
162
Am79C978
AMD [ AMD ]
