CSR78: Transmit Ring Length
work interface is operating in full-
duplex mode, receive DMA will
be requested as soon as either
the RCVFW threshold is reached
or a complete valid receive frame
is detected (regardless of length).
When the FDRPAD (BCR9, bit 2)
is set and the Am79C978 control-
ler is in full-duplex mode, in order
for receive DMA to be performed
for a new frame at least 64 bytes
must have been received. This
effectively disables the runt pack-
et accept feature in full duplex.
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0 XMTRL
Transmit Ring Length. Contains
the two’s complement of the
transmit descriptor ring length.
This register is initialized during
the Am79C978 controller’s initial-
ization routine based on the value
in the TLEN field of the initializa-
tion block. However, this register
can be manually altered. The ac-
tual transmit ring length is defined
by the current value in this regis-
ter. The ring length can be de-
fined as any value from 1 to
65535.
When operating in the NO-SRAM
mode (no SRAM enabled), the
Bus Receive FIFO and the MAC
Receive operate like a single
FIFO and the watermark value
selected by RCVFW[1:0] sets the
number of bytes that must be
present in the FIFO before re-
ceive DMA is requested.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
When operating with the SRAM,
the Bus Receive FIFO, and the
MAC Receive FIFO operate inde-
pendently on the bus side and
MAC side of the SRAM, respec-
tively. In this case, the watermark
value set by RCVFW[1:0] sets the
number of bytes that must be
present in the Bus Receive FIFO
only. See Table 32.
CSR80: DMA Transfer Counter and FIFO Threshold
Control
Bit
Name
Description
31-16 RES
15-14 RES
Reserved locations. Written as
zeros and read as undefined.
Reserved locations. Written as
zeros and read as undefined.
Table 32. Receive Watermark Programming
13-12 RCVFW[1:0] Receive
FIFO
Watermark.
RCVFW[1:0]
Bytes Received
RCVFW controls the point at
which receive DMA is requested
in relation to the number of re-
ceived bytes in the Receive FIFO.
RCVFW specifies the number of
bytes which must be present
(once the frame has been verified
as a non-runt) before receive
DMA is requested. Note, howev-
er, that if the network interface is
operating in half-duplex mode, in
order for receive DMA to be per-
formed for a new frame at least
64 bytes must have been re-
ceived. This effectively avoids
having to react to receive frames
which are runts or suffer a colli-
sion during the slot time (512 bit
times). If the Runt Packet Accept
feature is enabled or if the net-
00
01
10
11
16
64
112
Reserved
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set.
RCVFW[1:0] is set to a value of
01b (64 bytes) after H_RESET or
S_RESET and is unaffected by
STOP.
11-10 XMTSP[1:0] Transmit Start Point. XMTSP
controls the point at which pream-
ble transmission attempts to com-
mence in relation to the number
of bytes written to the MAC
Transmit FIFO for the current
138
Am79C978
AMD [ AMD ]
