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AM79C978KC/W 参数 Datasheet PDF下载

AM79C978KC/W图片预览
型号: AM79C978KC/W
PDF下载: 下载PDF文件 查看货源
内容描述: 单芯片1/10 Mbps的PCI家庭网络控制器 [Single-Chip 1/10 Mbps PCI Home Networking Controller]
分类和应用: 控制器PC
文件页数/大小: 261 页 / 3499 K
品牌: AMD [ AMD ]
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system may insert into an  
Am79C978 controller master  
transfer. If this value of bus laten-  
cy is exceeded, then a MERR will  
be indicated in CSR0, bit 11, and  
an interrupt may be generated,  
depending upon the setting of the  
MERRM bit (CSR3, bit 11) and  
the IENA bit (CSR0, bit 6).  
sions encountered by the  
receiver since the last reset of the  
counter.  
RCC will roll over to a count of 0  
from the value 65535. The  
RCVCCO bit of CSR4 (bit 5) will  
be set each time that this occurs.  
These bits are read accessible al-  
ways. RCC is read only, write op-  
erations are ignored. RCC is  
The value in this register is inter-  
preted as the unsigned number of  
bus clock periods divided by two,  
(i.e., the value in this register is  
given in 0.1 ms increments). For  
example, the value 0600h (1536  
decimal) will cause a MERR to be  
indicated after 153.6 ms of bus  
latency. A value of 0 will allow an  
infinitely long bus latency, i.e.,  
bus timeout error will never oc-  
cur.  
cleared  
by  
H_RESET  
or  
S_RESET, or by setting the  
STOP bit.  
CSR116: OnNow Power Mode Register  
Note: Bits 15-0 in this register are programmable  
through the EEPROM.  
Bit  
Name  
Description  
31-16 RES  
Reserved locations. Written as  
zeros and read as undefined.  
These bits are read/write acces-  
sible only when either the STOP  
or the SPND bit is set. This regis-  
ter is set to 0600h by H_RESET  
or S_RESET and is unaffected by  
STOP.  
10 PME_EN_OVR PME_EN Overwrite. When this  
bit is set and the MPMAT or  
LCDET bit is set, the PME pin will  
always be asserted regardless of  
the state of the PME_EN bit.  
CSR112: Missed Frame Count  
These bits are read/write accessi-  
ble only when either the STOP bit  
or the SPND bit is set. Cleared by  
H_RESET and is not affected by  
S_RESET or setting the STOP  
bit.  
Bit  
Name  
Description  
31-16 RES  
15-0 MFC  
Reserved locations. Written as  
zeros and read as undefined.  
Missed Frame Count. Indicates  
the number of missed frames.  
9
LCDET  
Link Change Detected. This bit is  
set when the MII auto-polling log-  
ic detects a change in link status  
and the LCMODE bit is set.  
MFC will roll over to a count of 0  
from the value 65535. The MFCO  
bit of CSR4 (bit 8) will be set each  
time that this occurs.  
LCDET is cleared when power is  
initially applied (POR).  
Read accessible always. MFC is  
read only, write operations are ig-  
nored. MFC is cleared by  
H_RESET, or S_RESET or by  
setting the STOP bit.  
This bit is always read/write ac-  
cessible.  
8
LCMODE  
Link Change Wake-up Mode.  
When this bit is set to 1, the  
LCDET bit gets set when the MII  
auto polling logic detects a Link  
Change.  
CSR114: Receive Collision Count  
Bit  
Name  
Description  
31-16 RES  
15-0 RCC  
Reserved locations. Written as  
zeros and read as undefined.  
Read/Write accessible only when  
either the STOP bit or the SPND  
bit is set. Cleared by H_RESET  
and is not affected by S_RESET  
or setting the STOP bit.  
Receive Collision Count. Indi-  
cates the total number of colli-  
142  
Am79C978