DMABC register is undefined un-
til written.
CSR89: Chip ID Register Upper
Bit
Name
Description
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
31-16 RES
15-12 VER
Reserved locations. Read as un-
defined.
Version. This 4-bit pattern is
silicon-revision dependent.
CSR88: Chip ID Register Lower
Read accessible only when either
the STOP or the SPND bit is set.
VER is read only. Write opera-
tions are ignored.
Bit
Name
Description
31-28 VER
Version. This 4-bit pattern is
silicon-revision dependent.
11-0 PARTIDU
Upper 12 bits of the Am79C978
controller part number, i.e., 0010
0110 0010b (262h).
Read accessible only when either
the STOP or the SPND bit is set.
VER is read only. Write opera-
tions are ignored.
Read accessible only when either
the STOP or the SPND bit is set.
VER is read only. PARTIDU is
read only. Write operations are
ignored.
27-12 PARTID
Part number. The 16-bit code for
the Am79C978 controller is
0010 0110 0010 0110 (2626h).
This register is exactly the same
as the Device ID register in the
JTAG description. However, this
part number is different from that
stored in the Device ID register in
the PCI configuration space.
CSR92: Ring Length Conversion
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0 RCON
Ring Length Conversion Regis-
ter. This register performs a ring
length conversion from an encod-
ed value as found in the initializa-
tion block to a two’s complement
value used for internal counting.
By writing bits 15-12 with an en-
coded ring length, a two’s com-
plemented value is read. The
RCON register is undefined until
written.
Read accessible only when either
the STOP or the SPND bit is set.
PARTID is read only. Write oper-
ations are ignored.
11-1 MANFID
Manufacturer ID. The 11-bit man-
ufacturer code for AMD is
00000000001b. This code is per
the JEDEC Publication 106-A.
Note that this code is not the
same as the Vendor ID in the PCI
configuration space.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
Read accessible only when either
the STOP or the SPND bit is set.
VER is read only. MANFID is
read only. Write operations are
ignored.
CSR100: Bus Timeout
Bit
Name
Description
0
ONE
Always a logic 1.
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
Read accessible only when either
the STOP or the SPND bit is set.
VER is read only. ONE is read
only. Write operations are ig-
nored.
15-0 MERRTO
This register contains the value of
the longest allowable bus latency
(interval between assertion of
REQ and assertion of GNT) that a
Am79C978
141
AMD [ AMD ]
