When MFCO is set, INTA is as-
serted if IENA is 1 and the mask
bit MFCOM is 0.
This bit is always read/write ac-
cessible. RCVCCO is cleared by
the host by writing a 1. Writing a
0 has no effect. RCVCCO is
This bit is always read/write ac-
cessible. MFCO is cleared by the
host by writing a 1. Writing a 0
has no effect. MFCO is cleared
by H_RESET, S_RESET, or by
setting the STOP bit.
cleared
by
H_RESET,
S_RESET, or by setting the
STOP bit.
4
RCVCCOM Receive Collision Counter Over-
flow Mask. If RCVCCOM is set,
the RCVCCO bit will be masked
and unable to set the INTR bit.
8
MFCOM
Missed Frame Counter Overflow
Mask. If MFCOM is set, the
MFCO bit will be masked and un-
able to set the INTR bit.
This bit is always read/write ac-
cessible. RCVCCOM is set to 1
by H_RESET or S_RESET and is
not affected by the STOP bit.
This bit is always read/write ac-
cessible. MFCOM is set to 1 by
H_RESET or S_RESET and is
not affected by the STOP bit.
3
TXSTRT
Transmit Start status is set by the
Am79C978 controller whenever it
begins transmission of a frame.
7
UINTCMD User
Interrupt
Command.
UINTCMD can be used by the
host to generate an interrupt un-
related to any network activity.
When UINTCMD is set, INTA is
asserted if IENA is set to 1. Write
a 1 to UINT to clear UINTCMD
and stop interrupts.
When TXSTRT is set, INTA is as-
serted if IENA is 1 and the mask
bit TXSTRTM is 0.
This bit is always read/write ac-
cessible. TXSTRT is cleared by
the host by writing a 1. Writing a
0 has no effect. TXSTRT is
This bit is always read/write ac-
cessible. UINTCMD is cleared by
H_RESET or S_RESET or by
setting the STOP bit.
cleared
by
H_RESET,
S_RESET, or by setting the
STOP bit.
2
TXSTRTM Transmit Start Mask. If TX-
STRTM is set, the TXSTRT bit
will be masked and unable to set
the INTR bit.
6
UINT
User Interrupt. UINT is set by the
Am79C978 controller after the
host has issued a user interrupt
command by setting UINTCMD
(CSR4, bit 7) to 1.
This bit is always read/write ac-
cessible. TXSTRTM is set to 1 by
H_RESET or S_RESET and is
not affected by the STOP bit.
This bit is always read/write ac-
cessible. UINT is cleared by the
host by writing a 1. Writing a 0
has no effect. UINT is cleared by
H_RESET or S_RESET or by
setting the STOP bit.
1-0
RES
Reserved locations. Written as
zeros and read as undefined.
CSR5: Extended Control and Interrupt 1
5
RCVCCO Receive Collision Counter Over-
flow is set by the Am79C978 con-
troller when the Receive Collision
Counter (CSR114 and CSR115)
has wrapped around.
Certain bits in CSR5 indicate the cause of an interrupt.
The register is designed so that these indicator bits are
cleared by writing ones to those bit locations. This
means that the software can read CSR5 and write back
the value just read to clear the interrupt condition.
Bit
Name
Description
When RCVCCO is set, INTA is
asserted if IENA is 1 and the
mask bit RCVCCOM is 0.
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
Am79C978
119
AMD [ AMD ]
