14-13 DATA_SCALE
Data Scale. This 2-bit read-only
These bits can be written and
read, but their contents have no
effect on the operation of the de-
vice.
field indicates the scaling factor
to be used when interpreting the
value of the Data register. The
value and meaning of this field
will vary depending on the
DATA_SCALE field.
These bits are always read/write
accessible.
PCI PMCSR Bridge Support Extensions Register
Offset 46h
These bits are read only.
Bit
Name
Description
12-9
DATA_SEL Data Select. This optional 4-bit
field is used to select which data
is reported through the Data reg-
ister and DATA_SCALE field.
7-0 PMCSR_BSE The PCI PMCSR Bridge Support
Extensions Register is an 8-bit
register. PMCSR Bridge Support
Extensions are not supported.
This register has a default value
of 00h.
These bits are always read/write
accessible. Sticky bit. These bits
are reset by POR. H_RESET,
S_RESET, or setting the STOP
bit has no effect.
The PCI PMCSR Bridge Support
Extensions register is located at
offset 46h in the PCI Configura-
tion Space. These bits are read
only.
8
PME_EN
PME Enable. When
a
1,
PME_EN enables the function to
assert PME. When a 0, PME as-
sertion is disabled.
PCI Data Register
Offset 47h
This bit defaults to “0” if the func-
tion does not support PME gener-
ation from D3cold.
Note: All bits of this register are loaded from the
EEPROM. The register is aliased to lower bytes of the
BCR37-BCR44 for testing purposes.
Bit
Name
Description
If the function supports PME from
D3cold, then this bit is sticky and
must be explicitly cleared by the
operating system each time the
operating system is initially load-
ed.
7-0
DATA_REG The PCI Data Register is an 8-bit
register. Refer to the “PCI Bus
Power Management Interface
Specification” version 1.0 for a
more detailed description of this
register.
This bit is always read/write ac-
cessible. Sticky bit. This bit is re-
The PCI DATA register is located
at offset 47h in the PCI Configu-
ration Space. It is read only.
set
by
POR.
H_RESET,
S_RESET, or setting the STOP
bit has no effect.
7-2
RES
Reserved locations. These bits
are read only.
RAP Register
The RAP (Register Address Pointer) register is used to
gain access to CSR and BCR registers on board the
Am79C978 controller. The RAP contains the address
of a CSR or BCR.
1-0 PWR_STATE Power State. This 2-bit field is
used both to determine the cur-
rent power state of a function and
to set the function into a new
power state. The definition of the
field values is given below.
As an example of RAP use, consider a read access to
CSR4. In order to access this register, it is necessary
to first load the value 0004h into the RAP by performing
a write access to the RAP offset of 12h (12h when WIO
mode has been selected, 14h when DWIO mode has
been selected). Then a second access is performed,
this time to the RDP offset of 10h (for either WIO or
DWIO mode). The RDP access is a read access, and
00b - D0.
01b - D1.
10b - D2.
11b - D3.
Am79C978
111
AMD [ AMD ]
