since RAP has just been loaded with the value of 0004h,
the RDP read will yield the contents of CSR4. A read of
the BDP at this time (offset of 16h when WIO mode has
been selected, 1Ch when DWIO mode has been select-
ed) will yield the contents of BCR4, since the RAP is
used as the pointer into both BDP and RDP space.
This bit is always read accessible
only. Write operations are ig-
nored.
14
13
RES
Reserved locations. This bit is al-
ways
read/write
accessible.
Read returns zero.
RAP: Register Address Port
CERR
Collision Error. Collision Error is
set by the Am79C978 controller
when the device operates in half-
duplex mode and the collision in-
puts to the GPSI port fail to acti-
vate within 20 network bit times
after the chip terminates trans-
mission (SQE Test). This feature
is a transceiver test feature.
CERR reporting is disabled when
the GPSI port is active and the
Am79C978 controller operates in
full-duplex mode.
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-8
7-0
RES
RAP
Reserved locations. Read and
written as zeros.
Register Address Port. The value
of these 8 bits determines which
CSR or BCR will be accessed
when an I/O access to the RDP
or BDP port, respectively, is per-
formed.
When the MII port is selected,
CERR is only reported when the
external PHY is operating as a
half-duplex 10BASE-T PHY.
A write access to undefined CSR
or BCR locations may cause un-
expected reprogramming of the
Am79C978 control registers. A
read access will yield undefined
values.
CERR assertion will not result in
an interrupt being generated.
CERR assertion will set the ERR
bit.
These bits are always read/write
accessible. RAP is cleared by
H_RESET or S_RESET and is
unaffected by setting the STOP
bit.
This bit is always read/write ac-
cessible. CERR is cleared by the
host by writing a 1. Writing a 0
has no effect. CERR is cleared by
H_RESET, S_RESET, or by set-
ting the STOP bit.
Control and Status Registers (CSRs)
The CSR space is accessible by performing accesses
to the RDP (Register Data Port). The particular CSR
that is read or written during an RDP access will depend
upon the current setting of the RAP. RAP serves as a
pointer into the CSR space.
12
MISS
Missed Frame. Missed Frame is
set by the Am79C978 controller
when it has lost an incoming re-
ceive frame resulting from a Re-
ceive Descriptor not being
available. This bit is the only im-
mediate indication that receive
data has been lost since there is
no current receive descriptor.
The Missed Frame Counter
(CSR112) also increments each
time a receive frame is missed.
CSR0: Controller Status and Control Register
Certain bits in CSR0 indicate the cause of an interrupt.
The register is designed so that these indicator bits are
cleared by writing ones to those bit locations. This
means that the software can read CSR0 and write back
the value just read to clear the interrupt condition.
Bit
Name
Description
When MISS is set, INTA is as-
serted if IENA is 1 and the mask
bit MISSM (CSR3, bit 12) is 0.
MISS assertion will set the ERR
bit, regardless of the settings of
IENA and MISSM.
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15
ERR
Error. Error is set by the OR of
CERR, MISS, and MERR. ERR
remains set as long as any of the
error flags are true.
112
Am79C978
AMD [ AMD ]
