controller will only respond to ac-
cesses to the Expansion ROM
when both ROMEN (PCI Expan-
sion ROM Base Address register,
bit 0) and MEMEN are set to 1.
Since MEMEN also enables the
memory mapped access to the
Am79C978 I/O resources, the
PCI Memory Mapped I/O Base
Address register must be pro-
grammed with an address so that
the device does not claim cycles
not intended for it.
• In master mode, during the data
phase of all memory read com-
mands.
In master mode, during the data
phase of the memory write com-
mand, the Am79C978 controller
sets the PERR bit if the target re-
ports a data parity error by as-
serting the PERR signal.
PERR is not effected by the state
of the Parity Error Response en-
able bit (PCI Command register,
bit 6).
MEMEN is cleared by H_RESET
and is not effected by S_RESET
or by setting the STOP bit.
PERR is set by the Am79C978
controller and cleared by writing a
1. Writing a 0 has no effect.
PERR is cleared by H_RESET
and is not affected by S_RESET
or by setting the STOP bit.
0
IOEN
I/O Space Access Enable. The
Am79C978 controller will ignore
all I/O accesses when IOEN is
cleared. The host must set IOEN
before the first I/O access to the
device. The PCI I/O Base Ad-
dress register must be pro-
grammed with a valid I/O address
before setting IOEN.
14
13
12
SERR
Signaled SERR. SERR is set
when the Am79C978 controller
detects an address parity error
and both SERREN and PERREN
(PCI Command register, bits 8
and 6) are set.
IOEN is cleared by H_RESET
and is not effected by S_RESET
or by setting the STOP bit.
SERR is set by the Am79C978
controller and cleared by writing a
1. Writing a 0 has no effect.
SERR is cleared by H_RESET
and is not affected by S_RESET
or by setting the STOP bit.
PCI Status Register
Offset 06h
The PCI Status register is a 16-bit register that contains
status information for the PCI bus related events. It is
located at offset 06h in the PCI Configuration Space.
RMABORT Received Master Abort. RM-
ABORT is set when the
Am79C978 controller terminates
a master cycle with a master
abort sequence.
Bit
Name
Description
15
PERR
Parity Error. PERR is set when
the Am79C978 controller detects
a parity error.
RMABORT is set by the
Am79C978
controller
and
The Am79C978 controller sam-
ples the AD[31:0], C/BE[3:0], and
the PAR lines for a parity error at
the following times:
cleared by writing a 1. Writing a 0
has no effect. RMABORT is
cleared by H_RESET and is not
affected by S_RESET or by set-
ting the STOP bit.
• In slave mode, during the ad-
dress phase of any PCI bus com-
mand.
RTABORT Received Target Abort. RT-
ABORT is set when a target ter-
minates an Am79C978 master
cycle with a target abort se-
quence.
• In slave mode, for all I/O, mem-
ory, and configuration write com-
mands that select the Am79C978
controller when data is trans-
ferred (TRDY and IRDY are as-
serted).
104
Am79C978
AMD [ AMD ]
