RTABORT is set by the
Am79C978 controller and
fast back-to-back transactions
with the first transaction address-
ing a different target.
cleared by writing a 1. Writing a 0
has no effect. RTABORT is
cleared by H_RESET and is not
affected by S_RESET or by set-
ting the STOP bit.
6-5
4
RES
Reserved locations. Read as
zero; write operations have no ef-
fect.
NEW_CAP New Capabilities. This bit indi-
cates whether this function imple-
11
STABORT Send Target Abort. Read as ze-
ro; write operations have no ef-
fect. The Am79C978 controller
will never terminate a slave ac-
cess with a target abort se-
quence.
ments
a
list of extended
capabilities such as PCI power
management. When set, this bit
indicates the presence of New
Capabilities. A value of 0 means
that this function does not imple-
ment New Capabilities.
STABORT is read only.
10-9
DEVSEL
Device Select Timing. DEVSEL
is set to 01b (medium), which
means that the Am79C978 con-
troller will assert DEVSEL two
clock periods after FRAME is as-
serted.
Read as one; write operations
have no effect. The Am79C978
controller supports the Linked
Additional Capabilities List.
3-0
RES
Reserved locations. Read as
zero; write operations have no ef-
fect.
DEVSEL is read only.
8
DATAPERR Data Parity Error Detected.
DATAPERR is set when the
Am79C978 controller is the cur-
rent bus master and it detects a
data parity error and the Parity
Error Response enable bit (PCI
Command register, bit 6) is set.
PCI Revision ID Register
Offset 08h
The PCI Revision ID register is an 8-bit register that
specifies the Am79C978 controller revision number.
The value of this register is 5Xh with the lower four bits
being silicon-revision dependent.
During the data phase of all
memory read commands, the
Am79C978 controller checks for
parity error by sampling AD[31:0],
C/BE[3:0], and the PAR lines.
During the data phase of all
memory write commands, the
Am79C978 controller checks the
PERR input to detect whether the
target has reported a parity error.
The PCI Revision ID register is located at offset 08h in
the PCI Configuration Space. It is read only.
PCI Programming Interface Register
Offset 09h
The PCI Programming Interface register is an 8-bit reg-
ister that identifies the programming interface of
Am79C978 controller. PCI does not define any specific
register-level programming interfaces for network de-
vices. The value of this register is 00h.
The PCI Programming Interface register is located at
offset 09h in the PCI Configuration Space. It is read only.
DATAPERR is set by the
Am79C978
controller
and
cleared by writing a 1. Writing a 0
has no effect. DATAPERR is
cleared by H_RESET and is not
affected by S_RESET or by set-
ting the STOP bit.
PCI Sub-Class Register
Offset 0Ah
The PCI Sub-Class register is an 8-bit register that iden-
tifies specifically the function of the Am79C978 control-
ler. The value of this register is 00h which identifies the
Am79C978 device as an Ethernet controller.
7
FBTBC
Fast Back-To-Back Capable.
Read as one; write operations
have no effect. The Am79C978
controller is capable of accepting
The PCI Sub-Class register is located at offset 0Ah in
the PCI Configuration Space. It is read only.
Am79C978
105
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