PCI Base-Class Register
6-0
LAYOUT
PCI configuration space layout.
Read as zeros; write operations
have no effect. The layout of the
PCI configuration space loca-
tions 10h to 3Ch is as shown in
Table 24.
Offset 0Bh
The PCI Base-Class register is an 8-bit register that
broadly classifies the function of the Am79C978 con-
troller. The value of this register is 02h, which classifies
the Am79C978 device as a networking controller.
PCI I/O Base Address Register
The PCI Base-Class register is located at offset 0Bh in
the PCI Configuration Space. It is read only.
Offset 10h
The PCI I/O Base Address register is a 32-bit register
that determines the location of the Am79C978 I/O re-
sources in all of I/O space. It is located at offset 10h in
the PCI Configuration Space.
PCI Latency Timer Register
Offset 0Dh
The PCI Latency Timer register is an 8-bit register that
specifies the minimum guaranteed time the Am79C978
controller will control the bus once it starts its bus mas-
tership period. The time is measured in clock cycles.
Every time the Am79C978 controller asserts FRAME at
the beginning of a bus mastership period, it will copy
the value of the PCI Latency Timer register into a
counter and start counting down. The counter willfreeze
at 0. When the system arbiter removes GNT while the
counter is non-zero, the Am79C978 controller will con-
tinue with its data transfers. It will only release the bus
when the counter has reached 0.
Bit
Name
Description
31-5
IOBASE
I/O base address most significant
27 bits. These bits are written by
the host to specify the location of
the Am79C978 I/O resources in
all of I/O space. IOBASE must be
written with a valid address be-
fore the Am79C978 controller
slave I/O mode is turned on by
setting the IOEN bit (PCI Com-
mand register, bit 0).
The PCI Latency Timer is only significant in burst trans-
actions, where FRAME stays asserted until the last data
phase. In a non-burst transaction, FRAME is only as-
serted during the address phase. The internal latency
counter will be cleared and suspended while FRAME is
deasserted.
When the Am79C978 controller
is enabled for I/O mode (IOEN is
set), it monitors the PCI bus for a
valid I/O command. If the value
on AD[31:5] during the address
phase of the cycles matches the
value of IOBASE, the Am79C978
controller will drive DEVSEL indi-
cating it will respond to the ac-
cess.
All eight bits of the PCI Latency Timer register are pro-
grammable. The host should read the Am79C978 PCI
MIN_GNTand PCI MAX_LATregisters to determine the
latency requirements for the device and then initialize
the Latency Timer register with an appropriate value.
The PCI Latency Timer register is located at offset 0Dh
in the PCI Configuration Space. It is read and written by
the host. The PCI Latency Timer register is cleared by
H_RESET and is not effected by S_RESET or by setting
the STOP bit.
IOBASE is read and written by
the host. IOBASE is cleared by
H_RESET and is not affected by
S_RESET or by setting the STOP
bit.
PCI Header Type Register
Offset 0Eh
4-2
IOSIZE
I/O size requirements. Read as
zeros; write operations have no
effect.
The PCI Header Type register is an 8-bit register that
describes the format of the PCI Configuration Space
locations 10h to 3Ch and that identifies a device to be
single or multi-function. The PCI Header Type register
is located at address 0Eh in the PCI Configuration
Space. It is read only.
IOSIZE indicates the size of the
I/O space the Am79C978 control-
ler requires. When the host writes
a value of FFFF FFFFh to the I/O
Base Address register, it will read
back a value of 0 in bits 4-2. That
indicates an Am79C978 I/O
space requirement of 32 bytes.
Bit
Name
Description
7
FUNCT
Single-function/multi-function de-
vice. Read as zero; write opera-
tions have no effect. The
Am79C978 controller is a single
function device.
1
RES
Reserved location. Read as zero;
write operations have no effect.
106
Am79C978
AMD [ AMD ]
