欢迎访问ic37.com |
会员登录 免费注册
发布采购

AM79C930VC/W 参数 Datasheet PDF下载

AM79C930VC/W图片预览
型号: AM79C930VC/W
PDF下载: 下载PDF文件 查看货源
内容描述: PCNET -Mobile的单芯片无线局域网媒体访问控制器 [PCnet-Mobile Single-Chip Wireless LAN Media Access Controller]
分类和应用: 个人通信控制器PCPCN无线无线局域网
文件页数/大小: 161 页 / 674 K
品牌: AMD [ AMD ]
 浏览型号AM79C930VC/W的Datasheet PDF文件第89页浏览型号AM79C930VC/W的Datasheet PDF文件第90页浏览型号AM79C930VC/W的Datasheet PDF文件第91页浏览型号AM79C930VC/W的Datasheet PDF文件第92页浏览型号AM79C930VC/W的Datasheet PDF文件第94页浏览型号AM79C930VC/W的Datasheet PDF文件第95页浏览型号AM79C930VC/W的Datasheet PDF文件第96页浏览型号AM79C930VC/W的Datasheet PDF文件第97页  
AMD  
P R E L I M I N A R Y  
(Generated from the internal signal stop_d, which indicates that an-  
tenna diversity operation has selected an antenna.) Assertion of  
ALOKI indicates the cessation of antenna diversity activity so that  
the incoming network signal can be tracked and decoded by the  
DPLL. ALOKI will be set to a 1 by the Am79C930 device when the  
conditions for stopping the antenna diversity switching as set up in  
the Baud Detect Circuit Control Registers, TCR17, TCR18, TCR20,  
TCR21, TCR22, and TCR23, and the RSSI Limit Register TIR28,  
and the CCA, and Antenna Diversity Control Register TCR28, have  
been met.  
TIR6: Interrupt Unmask Register 1  
Interrupt Unmask Register 1. Each bit in this register will  
unmask the corresponding interrupt of Interrupt Regis-  
ter 1 (TIR4) when the unmask bit is set to 1. When the  
unmask bit for any interrupt is set to 0, then the bit in the  
Interrupt register may still become set, but no interrupt  
to the 80188 embedded controller will occur.  
Bit  
Name  
Reset Value  
Description  
7
6
5
4
3
2
1
0
CHBSYCU  
ANTSWU  
MOREINTU  
TXCNTUN  
TXDONE  
CRCSU  
0
0
0
0
0
0
0
0
CHBSY Change Interrupt Unmask.  
Antenna Switch Interrupt Unmask.  
MOREINT Interrupt Unmask.  
TX Byte Count Interrupt Unmask.  
TXDONE Interrupt Unmask.  
CRC Start Interrupt Unmask.  
SDSNTU  
TXFBNU  
Start of Frame Delimiter Sent Interrupt Unmask.  
TX FIFO Byte Needed Interrupt Unmask.  
TIR7: Interrupt Unmask Register 2  
Interrupt Unmask Register 2.  
bit is set to 1. When the unmask bit for any interrupt is set  
to 0, then the bit in the Interrupt register may still become  
set, but no interrupt to the 80188 embedded controller  
will occur.  
Each bit in this register will unmask the corresponding  
interrupt of Interrupt Register 2 (TIR5) when the unmask  
Bit  
Name  
Reset Value  
Description  
7
6
5
4
3
2
1
0
RXCNTU  
CRC8GU  
CRC32GU  
RXFORU  
RXFBAU  
SDFU  
0
0
0
0
0
0
0
0
RX Byte Count Interrupt Unmask.  
CRC8 Good Interrupt Unmask.  
CRC32 Good Interrupt Unmask.  
RX FIFO Overrun Interrupt Unmask.  
RX FIFO Byte Available Interrupt Unmask.  
Start Delimiter Found Interrupt Unmask.  
Busy Channel Found Interrupt Unmask.  
Antenna Lock Interrupt Found Interrupt Unmask.  
BCFU  
ALOKIU  
Am79C930  
93  
 复制成功!