AMD
P R E L I M I N A R Y
TIR9: Transmit Status
Transmit Status register. Indicates the current status of
the Transmit portion of the TAI. Writes to these bits have
no effect.
Bit
Name
Reset Value
Description
7
TXCRC
0
Transmit CRC. TXCRC becomes set when the CRC is being ap-
pended to the end of the transmit frame. TXCRC is reset when the
transmission of the last bit of the CRC is completed.
6
TXSDD
0
Transmit Start Delimiter. TXSDD becomes set after the Start of
Frame Delimiter has been sent. This signal is deasserted when the
RESET pin is asserted or the CORESET bit is set to 1 (SIR0), when
the TXRES bit is set to 1 (TIR8), or when RXRES bit is set to 1
(TIR16), or when the RXS bit is set to 1 (TIR16), or the SRES bit is
set to 1 (TIR0). If a CRC is appended to the frame, then TXSDD will
be reset after the last bit of the CRC is appended to the frame.
5
Reserved
TXFC[3:0]
–
Reserved. Must be written as a 0. Reads of this bit produce
undefined data.
4–1
8h
Transmit FIFO Count. TXFC indicates the current count of the num-
ber of spaces available in the TX FIFO. The TX FIFO holds 8 bytes.
A TXFC value of “8h” indicates an empty TX FIFO, i.e., 8 spaces are
available. A TXFC value of “0h” indicates a full TX FIFO, i.e., 0
spaces are available.
0
TXBSY
0
TX Busy. This bit is set to 1 by the Am79C930 device when the
transmit operation begins and remains set until the transmission
has completed. Specifically, the TXBSY bit will be active whenever
the internal O_TX signal is active as indicated in the TX timing dia-
gram found in the Am79C930-based TX Power Ramp Control
section. When the TXC pin is configured as an input, then the
TXBSY signal will remain active until both the byte-wide TX FIFO
and the 16-bit serial FIFO have emptied. A write to this bit has
no effect.
TIR10: TX FIFO Data Register
This register is the TX FIFO Data Register. This
register allows direct access to the TX FIFO in the TAI.
When written, the TX FIFO write pointer is automatically
incremented. When read, the TX FIFO read pointer is
automatically incremented.
Bit
Name
Reset Value
Description
7:0
TXF[7:0]
–
Transmit FIFO data port. When written, data is placed into the sys-
tem side of the transmit FIFO. When read, data is removed from the
network side of the transmit FIFO. Reads of this register should be
for diagnostic purposes only and will not be necessary during nor-
mal operation. TX FIFO write and read pointers are automatically
incremented when writes and reads occur, respectively.
Am79C930
95
AMD [ AMD ]
