AMD
P R E L I M I N A R Y
TIR mapping with SIR1 bit 2 (EIOW) set to “1” = Ex-
panded TIR window mode. Note that the setting
EIOW = 1 is only allowed while operating in PCMCIA
mode. TIR uses 32 I/O addresses:
TIR
Register
Number
SIR1[1:0]
(TAI Bank
Select)
80188 Core
Address in
Memory
PCMCIA
I/O Address
TIR Register Name
Network Control
0
XX*
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
mem 400h
mem 401h
mem 402h
mem 403h
mem 404h
mem 405h
mem 406h
mem 407h
mem 408h
mem 409h
mem 40Ah
mem 40Bh
mem 40Ch
mem 40Dh
mem 40Eh
mem 40Fh
mem 410h
mem 411h
mem 412h
mem 413h
mem 414h
mem 415h
mem 416h
mem 417h
mem 418h
mem 419h
mem 41Ah
mem 41Bh
mem 41Ch
mem 41Dh
mem 41Eh
mem 41Fh
1
Network Status
2
Serial Device
3
Fast Serial Port Control
Interrupt Register 1
Interrupt Register 2
Interrupt Mask 1
4
5
6
7
Interrupt Mask 2
8
Transmit Control
9
Transmit Status
10
TX FIFO Data
11
Transmit Sequence Control
Byte Counter LSB
Byte Counter MSB
Byte Counter Limit LSB
Byte Counter Limit MSB
Receiver Control
12
13
14
15
16
17
Receiver Status
18
RX FIFO Data
19
Antenna Slot
20
CRC32 Correct Count LSB
CRC32 Correct Count MSB
CRC8 Correct Count LSB
CRC8 Correct Count MSB
Configuration Index
Configuration Data Port
Antenna Diversity & A/D
SAR
21
22
23
24
25
26
27
28
RSSI Lower Limit
USER Pin Data
29
30
31
Dummy Register
TEST Register
*XX = Don’t care.
88
Am79C930
AMD [ AMD ]
