AMD
P R E L I M I N A R Y
PCMCIA CCSR is RESET to a 0. If the STSCHGFN bit of TCR15
has been set to a 0, then the value that is written to this bit will be
inverted and driven to the STSTCHG pin of the Am79C930 device.
The value that is read from this bit always represents the inverse of
the current value of the STSTCHG pin of the Am79C930 device.
THIS FUNCTION IS ONLY AVAILABLE IN PCMCIA MODE.
The complete control of the function of the STSCHG/BALE pin is
described in the Multi-Function Pin section.
MIR10: Reserved
This register is reserved.
Bit
Name
Reset Value
Description
7:0
Reserved
–
Reserved. Must be written as a 0. Reads of this bit produce
undefined data.
MIR11: Reserved
This register is reserved.
Bit
Name
Reset Value
Description
7:0
Reserved
–
Reserved. Must be written as a 0. Reads of this bit produce
undefined data.
MIR12: Reserved
This register is reserved.
Bit
Name
Reset Value
Description
7:0
Reserved
–
Reserved. Must be written as a 0. Reads of this bit produce
undefined data.
MIR13: Reserved
This register is reserved.
Bit
Name
Reset Value
Description
7:0
Reserved
–
Reserved. Must be written as a 0. Reads of this bit produce
undefined data.
MIR14: Reserved
This register is reserved.
7:0
Reserved
–
Reserved. Must be written as a 0. Reads of this bit produce
undefined data.
MIR15: Reserved
This register is reserved.
Bit
Name
Reset Value
Description
7:0
Reserved
–
Reserved. Must be written as a 0. Reads of this bit produce
undefined data.
Am79C930
85
AMD [ AMD ]
