D A T A S H E E T
CONNECTION DIAGRAMS
This device is also available in Known Good Die (KGD) form. Refer to publication number 21551 for
more information.
NC
RESET#
A11
A10
A9
1
2
3
4
5
6
7
8
9
44 VCC
43 CE#
42 A12
41 A13
40 A14
39 A15
38 A16
37 A17
36 A18
35 A19
34 NC
A8
A7
A6
A5
A4 10
NC 11
NC 12
A3 13
SO
33 NC
32 A20
31 NC
A2 14
A1 15
30 WE#
29 OE#
28 RY/BY#
27 DQ7
26 DQ6
25 DQ5
24 DQ4
23 VCC
A0 16
DQ0 17
DQ1 18
DQ2 19
DQ3 20
VSS 21
VSS 22
PIN CONFIGURATION
LOGIC SYMBOL
A0–A20
=
21 Addresses
21
DQ0–DQ7 = 8 Data Inputs/Outputs
A0–A20
8
CE#
=
=
=
=
=
Chip Enable
DQ0–DQ7
WE#
Write Enable
OE#
Output Enable
CE#
OE#
RESET#
RY/BY#
Hardware Reset Pin, Active Low
Ready/Busy Output
WE#
V
=+5.0 V single power supply
(see Product Selector Guide for
device speed ratings and voltage
supply tolerances)
CC
RESET#
RY/BY#
V
=
=
Device Ground
SS
NC
Pin Not Connected Internally
6
Am29F016D
21444E6 November 1, 2006
AMD [ AMD ]
