P R E L I M I N A R Y
WRITE CYCLE WAVEFORMS
t1
t2
t3
t4
tW
CLKOUTA
65
A19–A0
Address
68
8
S6
S6
INVALID
Address
S6
14
7
6
30
AD15–AD0(a)
AD7–AD0(b)
,
Data
AD15–AD8(b)
Address
23
11
9
34
13
31
ALE
10
33
32
WR
12
41
20
5
20
31
WHB, WLB
BHE
87
BHE
67
99
LCS, UCS
18
16
MCS3–MCS0,
PCS6–PCS5,
PCS3–PCS0
17
35
20
31
DEN
98
21
20
DS
19
DT/R
(c)
22
(c)
22
3
S2–S0
Status
4
UZI
Notes:
a
b
c
Am186ED/EDLV microcontrollers in 16-bit mode
Am186ED/EDLV microcontrollers in 8-bit mode
Changes in t phase preceding next bus cycle if followed by read, INTA, or halt
Am186ED/EDLV Microcontrollers
69