P R E L I M I N A R Y
DRAM Write Cycle Timing with No-Wait States
t
t
t
t
t
t
1
4
1
2
3
4
CLKOUTA
AD[15:0]
5
7
30
Addr.
Data
68
101
Row
102
Column
A[17:1]
110
103
RAS
CAS
108
105
104
20
31
WR(a)
Note:
a
Write operations use the WR output connected to the DRAM write enable (WE) pin.
DRAM Write Cycle Timing With Wait State(s)
t
t
t
t
t
t
t
1
4
1
2
3
w
4
CLKOUTA
AD[15:0]
5
7
30
Addr.
Data
68
101
A[17:1]
RAS
Row
Column
107
110
102
109
104
105
CAS
20
31
WR(a)
Note:
a
Write operations use the WR output connected to the DRAM write enable (WE) pin.
72
Am186ED/EDLV Microcontrollers