P R E L I M I N A R Y
SWITCHING CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges
Write Cycle (20 MHz and 25 MHz)
Preliminary
Parameter
Description
20 MHz
Min
25 MHz
Min
No.
Symbol
Max
Max
Unit
General Timing Responses
3
tCHSV
tCLSH
tCLAV
Status Active Delay
0
0
0
0
0
0
25
25
25
25
15
0
0
0
0
0
0
20
20
20
20
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
Status Inactive Delay
5
AD Address Valid Delay and BHE
Address Hold
6
tCLAX
tCLDV
tCHDX
tCHLH
tLHLL
7
Data Valid Delay
8
Status Hold Time
9
ALE Active Delay
25
20
10
11
12
13
14
16
17
18
19
20
21
22
23
99
ALE Width
tCLCL–10=40
tCLCL–10=30
tCHLL
tAVLL
ALE Inactive Delay
25
20
AD Address Valid to ALE Low(a)
AD Address Hold from ALE Inactive(a)
AD Address Valid to Clock High
MCS/PCS Active Delay
MCS/PCS Hold from Command Inactive(a)
MCS/PCS Inactive Delay
DEN Inactive to DT/R Low(a)
Control Active Delay 1(b)
DS Inactive Delay
tCLCH –2
tCLCH–2
tLLAX
tCHCL–2
tCHCL–2
tAVCH
tCLCSV
tCXCSX
tCHCSX
tDXDL
tCVCTV
tCVDEX
tCHCTV
tLHAV
0
0
0
25
25
0
20
20
tCLCH–2
tCLCH–2
0
0
0
0
0
15
25
25
0
15
20
20
0
0
Control Active Delay 2
ALE High to Address Valid
PCS Active to ALE Inactive
0
0
20
15
15
15
tPLAL
28
25
24
20
Write Cycle Timing Responses
30
31
32
33
34
35
41
65
67
68
87
98
tCLDOX
tCVCTX
tWLWH
tWHLH
tWHDX
tWHDEX
tDSHLH
tAVWL
Data Hold Time
Control Inactive Delay(b)
0
0
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WR Pulse Width
2tCLCL–10=90
tCLCH–2
tCLCL–10=40
tCLCH–3
tCLCH–2=21
tCLCL+tCHCL–3
0
2tCLCL–10=70
tCLCH–2
tCLCL–10=30
tCLCH–3
tCLCH–2=16
tCLCL+tCHCL–3
0
WR Inactive to ALE High(a)
Data Hold after WR(a)
WR Inactive to DEN Inactive(a)
DS Inactive to ALE Active
A Address Valid to WR Low
CLKOUTA High to LCS/UCS Valid
CLKOUTA High to A Address Valid
A Address Valid to WHB, WLB Low
tCHCSV
tCHAV
25
25
25
20
20
20
0
0
tAVBL
tCHCL–3
35
tCHCL–3
30
tDSHDIW DS High to Data Invalid—Write
Notes:
All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions
are with CL =50 pF. For switching tests, VIL=0.45 V and VIH =2.4 V, except at X1 where VIH =VCC – 0.5 V.
a
b
Testing is performed with equal loading on referenced pins.
This parameter applies to the DEN, DS, INTA1–INTA0, WR, WHB, and WLB signals.
Am186ED/EDLV Microcontrollers
67
AMD [ AMD ]
