P R E L I M I N A R Y
READ CYCLE WAVEFORMS
t1
t2
t3
t4
tW
CLKOUTA
66
Address
A19–A0
8
68
S6
S6
INVALID
Address
S6
14
1
6
AD15–AD0(a)
AD7–AD0(b)
,
Data
2
Address
AD15–AD8(b)
23
29
9
11
59
28
15
ALE
RD
10
24
25
26
12
27
5
41
BHE(a)
BHE
67
18
13
99
LCS, UCS
16
17
MCS1–MCS0,
PCS6–PCS5,
PCS3–PCS0
20
21
DEN, DS
DT/R
19
(c)
(c)
4
22
3
22
S2–S0
UZI
Status
Notes:
a
b
c
Am186ED/EDLV microcontrollers in 16-bit mode
Am186ED/EDLV microcontrollers in 8-bit mode
Changes in t phase preceding next bus cycle if followed by read, INTA, or halt.
66
Am186ED/EDLV Microcontrollers