P R E L I M I N A R Y
SWITCHING CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges
DRAM
Preliminary
Parameter
Description
General Timing Responses
20 MHz
25 MHz
33 MHz
40 MHz
No. Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Unit
101
tCHCAV CLKOUTA Low to Column
0
25
0
20
0
15
0
12
ns
Address Valid
102
103
104
105
106
107
108
tCLRA
tCHRX
tCHCA
tCLCX
tCHRA
tCLRX
tRP0W
CLKOUTA Low to RAS Active
CLKOUTA High to RAS Inactive
CLKOUTA High to CAS Active
CLKOUTA Low to CAS Inactive
CLKOUTA High to RAS Active
CLKOUTA Low to RAS Inactive
3
3
25
25
25
25
25
25
—
3
3
20
20
20
20
20
20
—
3
3
15
15
15
15
15
15
—
3
3
12
12
12
12
12
12
—
ns
ns
ns
ns
ns
ns
ns
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
RAS Inactive Pulse Width with 0
Wait States
60
50
40
30
109
110
111
tRP1W
tRD0W
tRD1W
RAS Inactive Pulse Width with 1 or
More Wait States
70
25
30
—
—
—
60
20
25
—
—
—
50
15
20
—
—
—
40
15
15
—
—
—
ns
ns
ns
RAS To Column Address Delay
Time with 0 Wait States
RAS to Column Address Delay
Time with 1 or More Wait States
As guaranteed by design, the following table shows the minimum time for RAS assertion to RAS assertion. These
minimums correlate to DRAM spec tRC
.
Wait States
0
1
2
3
40 MHz
33 MHz
25 MHz
20 MHz
90
110
130
150
170
130
150
170
190
150
170
190
210
110
130
150
70
Am186ED/EDLV Microcontrollers
AMD [ AMD ]
